Abstract: A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

Abstract: A semiconductor device for outputting data read from a read only storage device, includes a plurality of read only storage devices, each including memory cells, a plurality of selecting signal lines for transmitting selecting signals to the read only storage devices for indicating a read only storage device storing data to be read, an address signal line for transmitting an address signal to the read only storage devices for indicating an address of memory cells storing data to be read and a switching device. The switching device has an address storage circuit for storing address information of a defective memory cell and detecting whether or not selected memory cells include a defective memory cell, a data storage circuit for storing replacement data for memory cells including a defective memory cell, and a switching circuit.

Abstract: A semiconductor device is provided for outputting data read from a read only storage device. The semiconductor device includes a read only storage device including memory cells, an address signal line for transmitting an address signal to each read only storage device, and a switching device to which the address signal is inputted. The address signal indicates an address of memory cells storing data to be read. The switching device includes an address storage circuit, a bit storage circuit and a switching storage circuit. The address storage circuit stores address information of a defective memory cell of the read only storage devices and detects whether or not memory cells storing data selected by an address signal includes a defective memory cell. The bit storage circuit stores bit information indicating which bit of data stored in memory cells including a defective memory cell is defective, and outputs a controlling signal.

Abstract: A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

Abstract: An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is “L,” and negative logic is confirmed in the case where the output of the output buffer circuit is “H.

Abstract: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

Abstract: A communication device which is constructed so as to permit efficient mounting of cards such as printed boards, thereby enhancing convenience and economy and ensuring high-quality communications. A basic unit is constituted by a basic board having a common control section packaged thereon, and a basic back wiring board on which are arranged a basic card connector for mounting a detachable card unit for processing signals and a basic link connector for additionally connecting such a card unit and which has wiring formed on a substrate thereof. An extension unit is connected to the basic link connector to permit additional connection of the card unit.

Abstract: According to a conventional semiconductor memory device, in a replica circuit composed of a plurality of dummy bit lines, an off leakage current of a transistor has been significantly increased with the advance of a semiconductor microfabrication technology, so that the dummy bit line has not been able to be charged to a desired potential due to the off leakage current when charging. As a result of this, since a charging period or a discharging period of the dummy bit line is also different from a desired period, the optimal operation timing may not be set. In a dummy memory cell array, in order to connect a drain region 21 and a first dummy bit line 25, the first dummy bit line 25 is connected via contact and via holes 28 through 30 and metal electrodes 23 and 24, while a second dummy bit line 46 does not contact to a drain region 47.

Abstract: A process for producing olefin by catalytic cracking of hydrocarbon material characterized in employing zeolite of penta-sil type comprising rare earth elements and at least one of manganese or zirconium as a catalyst. It enables to produce light olefin such as ethylene, propylene, and so on with selectively high yield and with long term stability, by catalytic cracking of gaseous or liquid hydrocarbon as ingredients under lower temperature than the conventional method and suppressing by-product such as aromatic hydrocarbon or heavy substances.

Abstract: An electronic apparatus has a plug-in unit and a housing that can increase a number of optical modules connected thereto. In the plug-in unit, a first connector is connectable to an optical module connected to an optical cable. A connector housing accommodates the first connector and has an insertion part into which the optical module is inserted. An attachment lever is used for fixing the plug-in unit to the housing in which the plug-in unit is accommodated. The first connector is located on a back side of the plug-in unit opposite to a front side where the attachment lever is located.

Abstract: An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is “L,” and negative logic is confirmed in the case where the output of the output buffer circuit is “H.

Abstract: A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.

Abstract: An electronic apparatus has a plug-in unit and a housing that can increase a number of optical modules connected thereto. In the plug-in unit, a first connector is connectable to an optical module connected to an optical cable. A connector housing accommodates the first connector and has an insertion part into which the optical module is inserted. An attachment lever is used for fixing the plug-in unit to the housing in which the plug-in unit is accommodated. The first connector is located on a back side of the plug-in unit opposite to a front side where the attachment lever is located.

Abstract: A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.

Abstract: In view of the transistor off leakage increasing with device miniaturization, the invention provides a semiconductor integrated circuit capable of high-speed readout by eliminating the need for a charge replenishing transistor formerly required to hold a bit line at the “H” level, and thereby speeding up readout of stored data that causes the bit line to transition to the “L” level. To achieve this, a high-potential source line and a low-potential source line are provided. Then, the source of a memory cell is selectively connected to either the high-potential source line and the low-potential source line.

Abstract: The object of the present invention is directed to shorten a manufacturing TAT when changing a stored data of a mask ROM incorporated into a semiconductor integrated circuit device with multi-layered structure, and to improve a manufacturing yield. For example, when the semiconductor integrated circuit device comprising an interconnection layer with five layers are manufactured, when fabricating samples or prototypes where data to be written to the mask ROM is frequently changed, the manufacturing TAT is shortened by means of configuring a bit line as a fifth layer of metal interconnection layer of an uppermost layer, and an interlayer dielectric (ILD) layer just below it as a forming layer of a via hole for use in data writing.

Abstract: A semiconductor device wherein the data read time in the case of replacing a defective memory cell with an address storage circuit and a data storage circuit is equal to the data read time in the case of reading data from a memory cell array and chip area is small is provided.

Abstract: In view of the transistor off leakage increasing with device miniaturization, the invention provides a semiconductor integrated circuit capable of high-speed readout by eliminating the need for a charge replenishing transistor formerly required to hold a bit line at the “H” level, and thereby speeding up readout of stored data that causes the bit line to transition to the “L” level. To achieve this, a high-potential source line and a low-potential source line are provided. Then, the source of a memory cell is selectively connected to either the high-potential source line and the low-potential source line.

Abstract: By eliminating a current of bit lines which is generated regularly by an off-leak current in memory cells, the number of memory cells per bit line is made to increase, large storage capacity of the memory cell array is achieved, and a semiconductor memory device capable of reducing a chip area is provided. In order to achieve it, provided is a source line potential control circuit for setting a source potential of transistors included in the memory cells being selected by row selection signals at a ground potential, and for setting a source potential of the transistors included in the memory cells being set as a non-selection state by the row selection signals at a power potential. A potential difference between sources and drains of the transistors included in the memory cells of the non-selection state is thereby reduced, and the leakage current is eliminated.

Abstract: The object of the present invention is directed to shorten a manufacturing TAT when changing a stored data of a mask ROM incorporated into a semiconductor integrated circuit device with multi-layered structure, and to improve a manufacturing yield. For example, when the semiconductor integrated circuit device comprising an interconnection layer with five layers are manufactured, when fabricating samples or prototypes where data to be written to the mask ROM is frequently changed, the manufacturing TAT is shortened by means of configuring a bit line as a fifth layer of metal interconnection layer of an uppermost layer, and an interlayer dielectric (ILD) layer just below it as a forming layer of a via hole for use in data writing.