Abstract: An electronic apparatus includes an optical connector adapting unit to which optical connectors of external optical fibers are connected. The optical connector adapting unit includes a plurality of optical connector adapters which are diagonally arranged on the front side of the apparatus. The optical connectors of the external optical fibers are diagonally detachable from the optical connector adapters. In this electronic apparatus, a large number of optical connectors of optical fibers can be connected and arranged in a restricted space.

Abstract: By eliminating a current of bit lines which is generated regularly by an off-leak current in memory cells, the number of memory cells per bit line is made to increase, large storage capacity of the memory cell array is achieved, and a semiconductor memory device capable of reducing a chip area is provided. In order to achieve it, provided is a source line potential control circuit for setting a source potential of transistors included in the memory cells being selected by row selection signals at a ground potential, and for setting a source potential of the transistors included in the memory cells being set as a non-selection state by the row selection signals at a power potential. A potential difference between sources and drains of the transistors included in the memory cells of the non-selection state is thereby reduced, and the leakage current is eliminated.

Abstract: A semiconductor memory device capable of reading out data at a higher speed and occupying a decreased chip-area is provided. The device includes a bit line selection circuit including a plurality of first transistors for selecting a plurality of bit lines according to a plurality of column selection signals generated based on address signals, a bit line charging circuit including a plurality of second transistors for charging the plurality of bit lines, respectively, and a bit line grounding circuit including a plurality of third transistors for connecting the plurality of bit lines with a ground potential. This enables the decrease in a charging time during a bit line precharging operation and a discharging time during data reading-out operation.

Abstract: On a semiconductor substrate surface, a drain diffusion layer, which is in common to two transistors that make up a memory cell pair, is formed and source diffusion layers, for each of the transistors, respectively, are formed so as to sandwich the drain diffusion layer from both sides, a bit line is formed from a lower wiring layer and is connected to the drain diffusion layer, a source line is formed from the uppermost wiring layer, and the writing of information is performed by making a contact hole exist or non-existent immediately below the source line arranged from the uppermost wiring layer, in other words, by connection or non-connection of the source diffusion layer with the source line. By this arrangement, the TAT can be shortened and, since the capacitance of the bit line is not increased, high-speed operation with a short precharge time and discharge time for the bit line can be realized and the consumption power can be lessened.

Abstract: A transmission apparatus with flexible structure for introducing external cables that controls signal transmission efficiently. A cable connector for introducing a cable from the outside is fixed on a sub-printed circuit board. A main printed circuit board has a guide rail along which the sub-printed circuit board can be inserted reversely to change the direction from which the cable is introduced at the time of the sub-printed circuit board being housed. An enclosure has ducts for bunching cables. Transmission units are mounted in the enclosure.

Abstract: A communication device which is constructed so as to permit efficient mounting of cards such as printed boards, thereby enhancing convenience and economy and ensuring high-quality communications. A basic unit is constituted by a basic board having a common control section packaged thereon, and a basic back wiring board on which are arranged a basic card connector for mounting a detachable card unit for processing signals and a basic link connector for additionally connecting such a card unit and which has wiring formed on a substrate thereof. An extension unit is connected to the basic link connector to permit additional connection of the card unit.

Abstract: On a semiconductor substrate surface, a drain diffusion layer, which is in common to two transistors that make up a memory cell pair, is formed and source diffusion layers, for each of the transistors, respectively, are formed so as to sandwich the drain diffusion layer from both sides, a bit line is formed from a lower wiring layer and is connected to the drain diffusion layer, a source line is formed from the uppermost wiring layer, and the writing of information is performed by making a contact hole exist or non-existent immediately below the source line arranged from the uppermost wiring layer, in other words, by connection or non-connection of the source diffusion layer with the source line. By this arrangement, the TAT can be shortened and, since the capacitance of the bit line is not increased, high-speed operation with a short precharge time and discharge time for the bit line can be realized and the consumption power can be lessened.

Abstract: A transmission apparatus with flexible structure for introducing external cables that controls signal transmission efficiently. A cable connector for introducing a cable from the outside is fixed on a sub-printed circuit board. A main printed circuit board has a guide rail along which the sub-printed circuit board can be inserted reversely to change the direction from which the cable is introduced at the time of the sub-printed circuit board being housed. An enclosure has ducts for bunching cables. Transmission units are mounted in the enclosure.

Abstract: A semiconductor memory device capable of reading out data at a higher speed and occupying a decreased chip-area is provided. The device includes a bit line selection circuit including a plurality of first transistors for selecting a plurality of bit lines according to a plurality of column selection signals generated based on address signals, a bit line charging circuit including a plurality of second transistors for charging the plurality of bit lines, respectively, and a bit line grounding circuit including a plurality of third transistors for connecting the plurality of bit lines with a ground potential. This enables the decrease in a charging time during a bit line precharging operation and a discharging time during data reading-out operation.