Patents by Inventor Mitsuaki Katagiri
Mitsuaki Katagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11705432Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.Type: GrantFiled: July 1, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
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Publication number: 20210327856Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.Type: ApplicationFiled: July 1, 2021Publication date: October 21, 2021Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
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Patent number: 11081468Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.Type: GrantFiled: August 28, 2019Date of Patent: August 3, 2021Assignee: Micron Technology, Inc.Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
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Publication number: 20210066247Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.Type: ApplicationFiled: August 28, 2019Publication date: March 4, 2021Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
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Patent number: 10600762Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.Type: GrantFiled: June 20, 2019Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Dai Sasaki, Mitsuaki Katagiri, Satoshi Isa
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Publication number: 20190304955Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Applicant: Micron Technology, Inc.Inventors: Dai Sasaki, Mitsuaki Katagiri, Satoshi Isa
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Patent number: 10431566Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.Type: GrantFiled: August 6, 2018Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventors: Dai Sasaki, Mitsuaki Katagiri, Satoshi Isa
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Publication number: 20190013294Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.Type: ApplicationFiled: August 6, 2018Publication date: January 10, 2019Applicant: Micron Technology, Inc.Inventors: Dai Sasaki, Mitsuaki Katagiri, Satoshi Isa
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Patent number: 10115709Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.Type: GrantFiled: July 7, 2017Date of Patent: October 30, 2018Assignee: Micron Technology, Inc.Inventors: Dai Sasaki, Mitsuaki Katagiri, Satoshi Isa
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Patent number: 9595489Abstract: A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.Type: GrantFiled: December 17, 2013Date of Patent: March 14, 2017Assignee: Longitude Semiconductor S.a.r.l.Inventors: Mitsuaki Katagiri, Ken Iwakura, Yutaka Uematsu
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Patent number: 9589921Abstract: In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.Type: GrantFiled: March 10, 2014Date of Patent: March 7, 2017Assignee: PS4 LUXCO S.A.R.L.Inventors: Mitsuaki Katagiri, Yu Hasegawa, Satoshi Isa
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Patent number: 9418967Abstract: A semiconductor device includes a package substrate, an IF chip, and a core chip. The package substrate has: first electrodes aligned and disposed on a first rear surface; second electrodes aligned and disposed in the first direction (Y direction) on a first front surface; and wiring that electrically connects the first electrodes and the second electrodes. The IF chip has third electrodes bonded to the second electrodes. The core chip is connected to the IF chip. In the first direction, the length of the IF chip is more than that of the core chip but equal to or less than that of the package substrate. One of the first electrodes is disposed further toward the outside than a core chip end portion in the first direction. At least one of the second electrodes is disposed further toward the outside than the core chip end portion in the first direction.Type: GrantFiled: September 27, 2013Date of Patent: August 16, 2016Assignee: PS4 LUXCO S.A.R.L.Inventors: Kazutaka Koshiishi, Mitsuaki Katagiri, Satoshi Isa, Dai Sasaki
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Publication number: 20160027758Abstract: [Problem] To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320).Type: ApplicationFiled: March 10, 2014Publication date: January 28, 2016Applicant: PS4 LUXCO S.A.R.L.Inventors: Mitsuaki Katagiri, Yu Hasegawa
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Publication number: 20160027754Abstract: To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320).Type: ApplicationFiled: March 10, 2014Publication date: January 28, 2016Applicant: PS4 Luxco S.a.r.l.Inventors: Mitsuaki Katagiri, Yu Hasegawa, Satoshi Isa
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Publication number: 20150262974Abstract: Provided is a semiconductor device that is equipped with a package substrate on which wiring can be easily laid out. This semiconductor device is provided with a package substrate (3), an IF chip (1), and a core chip (2). The package substrate has: a plurality of first electrodes (4) that are aligned and disposed on a first rear surface; a plurality of second electrodes (9) that are aligned and disposed in the first direction (Y direction) on a first front surface; and wiring (23) that electrically connects the first electrodes (4) and the second electrodes (9) to each other. The IF chip has a plurality of third electrodes that are bonded to the second electrodes (9). The core chip is connected to the IF chip. In the first direction, the length of the IF chip is more than that of the core chip but equal to or less than that of the package substrate. At least one of the first electrodes (4) is disposed further toward the outside than a core chip end portion in the first direction.Type: ApplicationFiled: September 27, 2013Publication date: September 17, 2015Inventors: Kazutaka Koshiishi, Mitsuaki Katagiri, Satoshi Isa, Dai Sasaki
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Patent number: 9048221Abstract: A device has a first substrate having a first surface; a first electrode pad arranged on the first surface of the first substrate; a first insulator film provided on the first surface of the first substrate so that the first electrode pad is exposed; a first bump electrode provided on the first electrode pad and having a first diameter; and a second bump electrode provided on the first insulator film and having a second diameter smaller than the first diameter.Type: GrantFiled: November 7, 2012Date of Patent: June 2, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Yu Hasegawa, Mitsuaki Katagiri
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Patent number: 8970052Abstract: In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: October 9, 2013Date of Patent: March 3, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Yu Hasegawa, Mitsuaki Katagiri, Satoshi Isa, Ken Iwakura, Dai Sasaki
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Patent number: 8941237Abstract: A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.Type: GrantFiled: June 18, 2013Date of Patent: January 27, 2015Assignee: PS4 Luxco S.A.R.L.Inventors: Yu Hasegawa, Mitsuaki Katagiri
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Publication number: 20150022255Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.Type: ApplicationFiled: October 3, 2014Publication date: January 22, 2015Applicant: PS4 Luxco S.a.r.I.Inventors: Mitsuaki KATAGIRI, Hiroki FUJISAWA, Hiromasa TAKEDA, Ken IWAKURA, Yutaka UEMATSU, Go SHINKAI
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Patent number: 8853822Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.Type: GrantFiled: November 16, 2012Date of Patent: October 7, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Mitsuaki Katagiri, Hiroki Fujisawa, Hiromasa Takeda, Ken Iwakura, Yutaka Uematsu, Go Shinkai