Patents by Inventor Mitsuhiro Omura

Mitsuhiro Omura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11651969
    Abstract: An etching method according to one embodiment, includes alternately switching a first step and a second step. The first step introduces a first gas containing a fluorine atom without supplying radiofrequency voltage to form a surface layer on a surface of a target cooled at a temperature equal to or lower than a liquefaction temperature of the first gas. The second step introduces a second gas gaseous at the first temperature and different from the first gas, and supplies the radiofrequency voltage, to generate plasma from the second gas to etch the target by sputtering using the plasma.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: May 16, 2023
    Assignee: Kioxia Corporation
    Inventors: Chihiro Abe, Toshiyuki Sasaki, Hisataka Hayashi, Mitsuhiro Omura, Tsubasa Imamura
  • Publication number: 20230114349
    Abstract: An etching method according to one embodiment, includes alternately switching a first step and a second step. The first step introduces a first gas containing a fluorine atom without supplying radiofrequency voltage to form a surface layer on a surface of a target cooled at a temperature equal to or lower than a liquefaction temperature of the first gas. The second step introduces a second gas gaseous at the first temperature and different from the first gas, and supplies the radiofrequency voltage, to generate plasma from the second gas to etch the target by sputtering using the plasma.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Applicant: Kioxia Corporation
    Inventors: Chihiro ABE, Toshiyuki SASAKI, Hisataka HAYASHI, Mitsuhiro OMURA, Tsubasa IMAMURA
  • Patent number: 11367624
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes forming a recess in the first film using the second film as a mask. The second film includes a first layer having carbon and a second layer having carbon formed on the first layer. The second layer has a second carbon density lower than a first carbon density of the first layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 21, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Junichi Hashimoto, Kaori Narumiya, Kosuke Horibe, Soichi Yamazaki, Kei Watanabe, Yusuke Kondo, Mitsuhiro Omura, Takehiro Kondoh, Yuya Matsubara, Junya Fujita, Toshiyuki Sasaki
  • Publication number: 20220165753
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 26, 2022
    Applicant: Kioxia Corporation
    Inventor: Mitsuhiro OMURA
  • Patent number: 11289506
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 29, 2022
    Assignee: Kioxia Corporation
    Inventor: Mitsuhiro Omura
  • Publication number: 20210296137
    Abstract: A film processing method includes forming a target film, the target film having an upper surface. The method includes forming a carbon film on the upper surface of the target film. The method includes performing a first etching to format least one recess in the target film, with the carbon film serving as a mask. The method includes performing a second etching, by directing an ion beam through the at least one recess, to increase a depth of the at least one recess.
    Type: Application
    Filed: August 28, 2020
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Junichi HASHIMOTO, Mitsuhiro OMURA, Toshiyuki SASAKI
  • Publication number: 20210066090
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes forming a recess in the first film using the second film as a mask. The second film includes a first layer having carbon and a second layer having carbon formed on the first layer. The second layer has a second carbon density lower than a first carbon density of the first layer.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 4, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Junichi HASHIMOTO, Kaori NARUMIYA, Kosuke HORIBE, Soichi YAMAZAKI, Kei WATANABE, Yusuke KONDO, Mitsuhiro OMURA, Takehiro KONDOH, Yuya MATSUBARA, Junya FUJITA, Toshiyuki SASAKI
  • Publication number: 20210020450
    Abstract: An etching method according to one embodiment, includes alternately switching a first step and a second step. The first step introduces a first gas containing a fluorine atom without supplying radiofrequency voltage to form a surface layer on a surface of a target cooled at a temperature equal to or lower than a liquefaction temperature of the first gas. The second step introduces a second gas gaseous at the first temperature and different from the first gas, and supplies the radiofrequency voltage, to generate plasma from the second gas to etch the target by sputtering using the plasma.
    Type: Application
    Filed: March 16, 2020
    Publication date: January 21, 2021
    Applicant: Kioxia Corporation
    Inventors: Chihiro ABE, Toshiyuki Sasaki, Hisataka Hayashi, Mitsuhiro Omura, Tsubasa Imamura
  • Publication number: 20200212062
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
    Type: Application
    Filed: March 5, 2020
    Publication date: July 2, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Mitsuhiro OMURA
  • Patent number: 10153164
    Abstract: A method for manufacturing a semiconductor device includes forming a mask layer including a) one metal from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium, b) boron, and c) carbon on a layer to be etched. The mask layer is patterned. A hole or a groove is formed in the layer to be etched by performing dry etching on the layer to be etched using the patterned mask layer. The mask layer includes a first region and a second region. The first region includes boron and the second region includes boron such that a density of boron in the second region is different from a density of boron in the first region, or the first region includes carbon and the second region includes carbon such that a density of carbon in the second region is different from a density of carbon in the first region.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura
  • Patent number: 10026622
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mitsuhiro Omura, Tsubasa Imamura, Itsuko Sakai
  • Publication number: 20180166276
    Abstract: A method for manufacturing a semiconductor device includes forming a mask layer including a) one metal from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium, b) boron, and c) carbon on a layer to be etched. The mask layer is patterned. A hole or a groove is formed in the layer to be etched by performing dry etching on the layer to be etched using the patterned mask layer. The mask layer includes a first region and a second region. The first region includes boron and the second region includes boron such that a density of boron in the second region is different from a density of boron in the first region, or the first region includes carbon and the second region includes carbon such that a density of carbon in the second region is different from a density of carbon in the first region.
    Type: Application
    Filed: July 27, 2017
    Publication date: June 14, 2018
    Applicant: TOSHIBA MEMORY CORPORATON
    Inventors: Shinichi NAKAO, Shunsuke OCHIAI, Yusuke OSHIKI, Kei WATANABE, Mitsuhiro OMURA
  • Patent number: 9887093
    Abstract: A semiconductor device manufacturing method includes forming a first resist and a second resist on a stacked body that includes a plurality of first films and a plurality of second films, the second resist facing one or more side surfaces of the first resist; forming a third film in a slit between the first resist and the second resist, the third film covering the side surfaces of the first resist and defining exposed surfaces of the first resist not covered by the third film; performing a first etch of the stacked body from an upper surface using the first resist, the second resist, and the third film as a mask; selectively etching the one or more exposed surfaces of the first resist and the second resist; and performing a second etch of the stacked body from the upper surface using the first resist and the third film as a mask.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mitsuhiro Omura
  • Patent number: 9876022
    Abstract: A method for manufacturing a semiconductor device includes forming a resist film on a film to be processed. An upper portion of the film to be processed is processed using the resist film as a first mask. Tungsten or a tungsten compound is selectively formed on the resist film. A lower portion of the film to be processed is processed with a reducing gas using the tungsten or the tungsten compound as a second mask.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomo Hasegawa, Kazuhisa Matsuda, Toshiyuki Sasaki, Mitsuhiro Omura
  • Publication number: 20170301691
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Applicant: Toshiba Memory Corporation
    Inventor: Mitsuhiro Omura
  • Patent number: 9786679
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes forming a stopper film in a part of the mask layer. The method includes forming a plurality of mask holes in the mask layer. The mask holes include a first mask hole overlapping on the stopper film. The method includes, by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the stopper film, but not forming holes in the stacked body under the stopper film. The method includes forming memory films and channel bodies in the holes.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 10, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mitsuhiro Omura
  • Publication number: 20170271170
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 21, 2017
    Inventors: Mitsuhiro OMURA, Tsubasa IMAMURA, Itsuko SAKAI
  • Patent number: 9754793
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura, Kosuke Horibe, Atsuko Sakata, Junichi Wada, Soichi Yamazaki, Masayuki Kitamura, Yuya Matsubara
  • Patent number: 9728550
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 8, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mitsuhiro Omura
  • Patent number: 9620366
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched. The mask layer contains at least one type of a metal, boron, and carbon. The metal is selected from a group including tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium and iridium. A composition ratio of the metal is higher than a composition ratio of the boron and a composition ratio of the carbon. The method includes making a hole or a slit in the layer to be etched by performing a dry etching to the layer to be etched using the mask layer being patterned.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: April 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura