Patents by Inventor Mitsuhiro Omura
Mitsuhiro Omura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7846348Abstract: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; andType: GrantFiled: October 29, 2007Date of Patent: December 7, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuhiro Omura
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Patent number: 7799672Abstract: A semiconductor device includes: a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked therein, the stacked body including a staircase structure having the plurality of conductive layers processed into a staircase shape; an interlayer dielectric layer covering the staircase structure; and a contact electrode provided inside a contact hole penetrating through the interlayer dielectric layer, the contact hole penetrating through one of the staircase-shaped conductive layers, the contact electrode being in contact with a sidewall portion of the one of the staircase-shaped conductive layers exposed into the contact hole.Type: GrantFiled: August 21, 2009Date of Patent: September 21, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Hashimoto, Mitsuhiro Omura
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Publication number: 20100207240Abstract: A semiconductor device includes: a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked therein, the stacked body including a staircase structure having the plurality of conductive layers processed into a staircase shape; an interlayer dielectric layer covering the staircase structure; and a contact electrode provided inside a contact hole penetrating through the interlayer dielectric layer, the contact hole penetrating through one of the staircase-shaped conductive layers, the contact electrode being in contact with a sidewall portion of the one of the staircase-shaped conductive layers exposed into the contact hole.Type: ApplicationFiled: August 21, 2009Publication date: August 19, 2010Inventors: Junichi Hashimoto, Mitsuhiro Omura
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Publication number: 20100176440Abstract: A semiconductor device includes: a first layer; a second layer; a columnar structural unit; and a side portion. The second layer is provided on a major surface of the first layer. The columnar structural unit is conductive and aligned in the first layer and the second layer to pass through the major surface. The side portion is added to a side wall of the columnar structural unit on the second layer side of the major surface.Type: ApplicationFiled: November 9, 2009Publication date: July 15, 2010Inventor: Mitsuhiro OMURA
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Patent number: 7749913Abstract: A first silicon containing film, an organic material film, a second silicon containing film are formed. The second silicon containing film is patterned to have a narrow width pattern and a wide width pattern. The organic material film is patterned to have a narrow width pattern and a wide width pattern. A side wall is formed on a side surface of the second silicon containing film and the organic material film by coating with a third silicon containing film. The narrow width pattern of the second silicon containing film is removed by using a mask that covers the second silicon containing film patterned to have a wide width pattern and the side wall. Finally, the organic material film is removed.Type: GrantFiled: December 16, 2008Date of Patent: July 6, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Omura, Keisuke Kikutani, Yutaka Okamoto
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Publication number: 20100112801Abstract: A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces of the gate structure and the major surface of the semiconductor substrate, reforming portions of the first insulating film which cover the top surface of the gate structure and the major surface of the semiconductor substrate by an anisotropic plasma process using a gas not containing fluorine, and removing the reformed portions of the first insulating film.Type: ApplicationFiled: January 4, 2010Publication date: May 6, 2010Inventors: Mitsuhiro Omura, Nobuaki Yasutake
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Patent number: 7670891Abstract: A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces of the gate structure and the major surface of the semiconductor substrate, reforming portions of the first insulating film which cover the top surface of the gate structure and the major surface of the semiconductor substrate by an anisotropic plasma process using a gas not containing fluorine, and removing the reformed portions of the first insulating film.Type: GrantFiled: September 8, 2005Date of Patent: March 2, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Omura, Nobuaki Yasutake
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Publication number: 20100041235Abstract: A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of the silicon film by processing the silicon film until a part of the second insulating film is exposed by use of etch-back; removing the second insulating film; and performing dry etching by use of a fluorocarbon-based gas, to process the first insulating film by using the sidewall as a mask. The processing of the first insulating film includes applying on the substrate a self-bias voltage Vdc that satisfies a relational expression of Vdc<46x?890, where a film thickness of the silicon film that constitutes the sidewall is x nm (19.5?x?22.1).Type: ApplicationFiled: August 12, 2009Publication date: February 18, 2010Inventors: Junichi Hashimoto, Mitsuhiro Omura, Yasuyoshi Hyodo, Takamichi Tsuchiya
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Publication number: 20090305497Abstract: A method for fabricating a semiconductor device, includes: forming a first film pattern above a substrate; forming a plurality of second film patterns like sandwiching the first film pattern from both sides; forming a third film in such a way that an upper surface of the first film pattern and an upper surface and an exposed side surface of each of the plurality of second film patterns are coated with the third film; removing a portion of the third film until the upper surface of the first film pattern is exposed; removing, by a wet process, the first film pattern exposed after the portion of the third film is removed; and removing a remainder of the third film by a dry process after the first film pattern is removed.Type: ApplicationFiled: April 17, 2009Publication date: December 10, 2009Inventor: Mitsuhiro OMURA
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Publication number: 20090163030Abstract: A first silicon containing film, an organic material film, a second silicon containing film are formed. The second silicon containing film is patterned to have a narrow width pattern and a wide width pattern. The organic material film is patterned to have a narrow width pattern and a wide width pattern. A side wall is formed on a side surface of the second silicon containing film and the organic material film by coating with a third silicon containing film. The narrow width pattern of the second silicon containing film is removed by using a mask that covers the second silicon containing film patterned to have a wide width pattern and the side wall. Finally, the organic material film is removed.Type: ApplicationFiled: December 16, 2008Publication date: June 25, 2009Inventors: Mitsuhiro OMURA, Keisuke Kikutani, Yutaka Okamoto
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Publication number: 20090096007Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.Type: ApplicationFiled: October 2, 2008Publication date: April 16, 2009Inventors: Mitsuhiro OMURA, Satoshi NAGASHIMA, Katsunori YAHASHI, Jungo INABA, Daina INOUE
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Publication number: 20080138995Abstract: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; andType: ApplicationFiled: October 29, 2007Publication date: June 12, 2008Inventor: Mitsuhiro OMURA
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Publication number: 20080070328Abstract: A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming a film to be processed having a first film thickness on a semiconductor substrate; forming a region, within the film to be processed, having a second film thickness thinner than the first film thickness by processing a part of the film to be processed; processing the film to be processed having the region of the second film thickness formed therein by utilizing a dry etching method while a change in characteristic value of a plasma is monitored; detecting a first timing at which a member right under the region, within the film to be processed, which had the second film thickness before the processing performed by utilizing the dry etching method begins to be exposed in accordance with the change in characteristic value of the plasma during the processing performed by utilizing the dry etching method; and estimating a second timing right before a member right under a region, of the film to be prType: ApplicationFiled: August 10, 2007Publication date: March 20, 2008Inventor: Mitsuhiro Omura
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Patent number: 7232763Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.Type: GrantFiled: October 7, 2004Date of Patent: June 19, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Omura, Makiko Katano, Shoko Ito, Takaya Matsushita, Hisashi Kaneko
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Publication number: 20060057828Abstract: A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces of the gate structure and the major surface of the semiconductor substrate, reforming portions of the first insulating film which cover the top surface of the gate structure and the major surface of the semiconductor substrate by an anisotropic plasma process using a gas not containing fluorine, and removing the reformed portions of the first insulating film.Type: ApplicationFiled: September 8, 2005Publication date: March 16, 2006Inventors: Mitsuhiro Omura, Nobuaki Yasutake
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Patent number: 6951781Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a first metal wiring and a fuse, both being formed as the same level above the semiconductor substrate, a first insulating film formed on the first metal wiring and the fuse, the first insulating film having a first pad opening arriving at the first metal wiring, a second metal wiring formed at least within the first pad opening, the second metal wiring not extending above the fuse, a stopper film formed on the first insulating film and the second metal wiring, and a second insulating film formed above the stopper film. A second pad opening is formed to expose the second metal wiring by removing the second insulating film and the stopper film, a fuse opening is formed above at least the fuse by removing the second insulating film and the stopper film, and by removing the first insulating film incompletely.Type: GrantFiled: November 15, 2004Date of Patent: October 4, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Omura, Fumio Sato
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Publication number: 20050106866Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.Type: ApplicationFiled: October 7, 2004Publication date: May 19, 2005Inventors: Mitsuhiro Omura, Makiko Katano, Shoko Ito, Takaya Matsushita, Hisashi Kaneko
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Publication number: 20050087837Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a first metal wiring and a fuse, both being formed as the same level above the semiconductor substrate, a first insulating film formed on the first metal wiring and the fuse, the first insulating film having a first pad opening arriving at the first metal wiring, a second metal wiring formed at least within the first pad opening, the second metal wiring not extending above the fuse, a stopper film formed on the first insulating film and the second metal wiring, and a second insulating film formed above the stopper film. A second pad opening is formed to expose the second metal wiring by removing the second insulating film and the stopper film, a fuse opening is formed above at least the fuse by removing the second insulating film and the stopper film, and by removing the first insulating film incompletely.Type: ApplicationFiled: November 15, 2004Publication date: April 28, 2005Inventors: Mitsuhiro Omura, Fumio Sato
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Patent number: 6835999Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a first metal wiring and a fuse, both being formed as the same level above the semiconductor substrate, a first insulating film formed on the first metal wiring and the fuse, the first insulating film having a first pad opening arriving at the first metal wiring, a second metal wiring formed at least within the first pad opening, the second metal wiring not extending above the fuse, a stopper film formed on the first insulating film and the second metal wiring, and a second insulating film formed above the stopper film. A second pad opening is formed to expose the second metal wiring by removing the second insulating film and the stopper film, a fuse opening is formed above at least the fuse by removing the second insulating film and the stopper film, and by removing the first insulating film incompletely.Type: GrantFiled: June 11, 2003Date of Patent: December 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Omura, Fumio Sato
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Publication number: 20040012073Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a first metal wiring and a fuse, both being formed as the same level above the semiconductor substrate, a first insulating film formed on the first metal wiring and the fuse, the first insulating film having a first pad opening arriving at the first metal wiring, a second metal wiring formed at least within the first pad opening, the second metal wiring not extending above the fuse, a stopper film formed on the first insulating film and the second metal wiring, and a second insulating film formed above the stopper film. A second pad opening is formed to expose the second metal wiring by removing the second insulating film and the stopper film, a fuse opening is formed above at least the fuse by removing the second insulating film and the stopper film, and by removing the first insulating film incompletely.Type: ApplicationFiled: June 11, 2003Publication date: January 22, 2004Inventors: Mitsuhiro Omura, Fumio Sato