Patents by Inventor Mitsuhiro Omura

Mitsuhiro Omura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9105584
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first line pattern comprising a first film above an underlying layer, depositing a second film on a sidewall and a top surface of the first line pattern of the first film, etching the second film to eliminate the second film on the top surface of the first line pattern of the first film and leave the second film on the sidewall of the first line pattern of the first film, and removing the first line pattern to form a second line pattern of the second film above the underlying layer. The depositing the second film, etching the second film, and removing the first line pattern are sequentially performed within the same plasma processing device.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: August 11, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Omura, Toshiyuki Sasaki, Tsubasa Imamura, Kazuhisa Matsuda
  • Patent number: 9093261
    Abstract: A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material. The method includes etching the upper layer film after loading the semiconductor substrate into the processing chamber; forming a lift-off layer along an inner wall of the processing chamber with the semiconductor substrate loaded in the processing chamber; etching the uneasily-etched material and causing deposition of a reactive product of the uneasily-etched material along the lift-off layer; and cleaning, by removing the reactive product by removing the lift-off layer, the inner wall of the processing chamber after the semiconductor substrate is unloaded from the plasma etching apparatus.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: July 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Sasaki, Mitsuhiro Omura, Kazuhito Furumoto
  • Publication number: 20150104942
    Abstract: A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material. The method includes etching the upper layer film after loading the semiconductor substrate into the processing chamber; forming a lift-off layer along an inner wall of the processing chamber with the semiconductor substrate loaded in the processing chamber; etching the uneasily-etched material and causing deposition of a reactive product of the uneasily-etched material along the lift-off layer; and cleaning, by removing the reactive product by removing the lift-off layer, the inner wall of the processing chamber after the semiconductor substrate is unloaded from the plasma etching apparatus.
    Type: Application
    Filed: March 10, 2014
    Publication date: April 16, 2015
    Inventors: Toshiyuki SASAKI, Mitsuhiro OMURA, Kazuhito FURUMOTO
  • Publication number: 20150064913
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first line pattern comprising a first film above an underlying layer, depositing a second film on a sidewall and a top surface of the first line pattern of the first film, etching the second film to eliminate the second film on the top surface of the first line pattern of the first film and leave the second film on the sidewall of the first line pattern of the first film, and removing the first line pattern to form a second line pattern of the second film above the underlying layer. The depositing the second film, etching the second film, and removing the first line pattern are sequentially performed within the same plasma processing device.
    Type: Application
    Filed: January 3, 2014
    Publication date: March 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: MITSUHIRO OMURA, Toshiyuki SASAKI, Tsubasa IMAMURA, Kazuhisa MATSUDA
  • Publication number: 20150011089
    Abstract: According to one embodiment, a pattern formation method includes forming a layer above an underlying layer. The layer includes a block copolymer. The method further includes forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer, and selectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide.
    Type: Application
    Filed: March 10, 2014
    Publication date: January 8, 2015
    Inventors: Hiroshi Yamamoto, Tsubasa Imamura, Hisataka Hayashi, Mitsuhiro Omura
  • Publication number: 20140083979
    Abstract: A deposit removal method for removing deposits deposited on the surface of a pattern formed on a substrate by etching, includes an oxygen plasma treatment process for exposing the substrate to oxygen plasma while heating the substrate and a cycle treatment process for, after the oxygen plasma treatment process, repeating multiple cycles of a first period and a second period. In the first period, the substrate is exposed to a mixture of hydrogen fluoride gas and alcohol gas inside a processing chamber and the partial pressure of the alcohol gas is set to the first partial pressure. In the second period, the partial pressure of the alcohol gas is set to the second partial pressure lower than the first partial pressure by exhausting the inside of the processing chamber.
    Type: Application
    Filed: May 10, 2012
    Publication date: March 27, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Tahara, Eiichi Nishimura, Hiroshi Tomita, Tokuhisa Ohiwa, Hisashi Okuchi, Mitsuhiro Omura
  • Patent number: 8524609
    Abstract: An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device including providing a film to be processed above a semiconductor substrate, providing a negative-type resist and a photo-curable resist in order, pressing a main surface of a template onto the photo-curable resist, the main surface of the template having a concavo-convex pattern with a light shield portion provided on at least a part of a convex portion, irradiating the template with light from a back surface of the template, developing the negative-type resist and the photo-curable resist so as to print the concavo-convex pattern of the template on the negative-type resist and the photo-curable resist, and etching the film to be processed by using the concavo-convex pattern printed on the negative-type resist and the photo-curable resist as a mask.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Inada, Mitsuhiro Omura, Hisataka Hayashi
  • Patent number: 8513134
    Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Omura, Yumi Ohno, Takaya Matsushita, Tokuhisa Ohiwa
  • Patent number: 8460997
    Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: June 11, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Omura, Satoshi Nagashima, Katsunori Yahashi, Jungo Inaba, Daina Inoue
  • Publication number: 20120326223
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
    Type: Application
    Filed: January 6, 2012
    Publication date: December 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiro Omura
  • Publication number: 20120315758
    Abstract: According to one embodiment, a semiconductor device manufacturing method comprises mounting a supporting substrate on a front surface side of a silicon substrate having an interconnection layer and function elements formed on a front surface side, polishing a back surface side of the silicon substrate, forming a mask having an opening and an opening for a dummy hole having a diameter smaller than that of the above opening on the back surface side of the silicon substrate, etching portions exposed to the openings of the mask from the back surface side of the silicon substrate to form a via hole that reaches a part of the interconnection layer and form a dummy hole to an intermediate portion of the silicon substrate, and forming an interconnection material in the via hole.
    Type: Application
    Filed: March 21, 2012
    Publication date: December 13, 2012
    Inventors: Noriko SAKURAI, Mitsuhiro Omura, Toshiyuki Sasaki, Itsuko Sakai
  • Publication number: 20120214308
    Abstract: An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device including providing a film to be processed above a semiconductor substrate, providing a negative-type resist and a photo-curable resist in order, pressing a main surface of a template onto the photo-curable resist, the main surface of the template having a concavo-convex pattern with a light shield portion provided on at least a part of a convex portion, irradiating the template with light from a back surface of the template, developing the negative-type resist and the photo-curable resist so as to print the concavo-convex pattern of the template on the negative-type resist and the photo-curable resist, and etching the film to be processed by using the concavo-convex pattern printed on the negative-type resist and the photo-curable resist as a mask.
    Type: Application
    Filed: September 12, 2011
    Publication date: August 23, 2012
    Inventors: Satoshi INADA, Mitsuhiro OMURA, Hisataka HAYASHI
  • Patent number: 8198669
    Abstract: A semiconductor device includes: a first layer; a second layer; a columnar structural unit; and a side portion. The second layer is provided on a major surface of the first layer. The columnar structural unit is conductive and aligned in the first layer and the second layer to pass through the major surface. The side portion is added to a side wall of the columnar structural unit on the second layer side of the major surface.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiro Omura
  • Patent number: 8158509
    Abstract: A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces of the gate structure and the major surface of the semiconductor substrate, reforming portions of the first insulating film which cover the top surface of the gate structure and the major surface of the semiconductor substrate by an anisotropic plasma process using a gas not containing fluorine, and removing the reformed portions of the first insulating film.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: April 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Omura, Nobuaki Yasutake
  • Publication number: 20120021605
    Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.
    Type: Application
    Filed: January 25, 2011
    Publication date: January 26, 2012
    Inventors: Mitsuhiro OMURA, Yumi Ohno, Takaya Matsushita, Tokuhisa Ohiwa
  • Publication number: 20120009786
    Abstract: A plasma processing method in which performing a plasma etching on metal layers formed on a substrate is conducted to form a pattern having the metal layers in a stacked structure, and then a deposit containing a metal that forms the metal layers and being deposited on a sidewall portion of the pattern is removed, the method includes: forming a protective layer by forming an oxide or chloride of the metal on sidewall portions of the metal layers; removing the deposit by applying a plasma of a gas containing fluorine atoms; and reducing the oxide or chloride of the metal by applying a plasma containing hydrogen after forming the protective layer and removing the deposit.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 12, 2012
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOKYO ELECTRON LIMITED
    Inventors: Shigeru TAHARA, Eiichi Nishimura, Fumiko Yamashita, Hiroshi Tomita, Tokuhisa Ohiwa, Hisashi Okuchi, Mitsuhiro Omura
  • Patent number: 7943522
    Abstract: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; and
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: May 17, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiro Omura
  • Publication number: 20110097888
    Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.
    Type: Application
    Filed: January 3, 2011
    Publication date: April 28, 2011
    Inventors: Mitsuhiro Omura, Satoshi Nagashima, Katsunori Yahashi, Jungo Inaba, Daina Inoue
  • Patent number: 7906434
    Abstract: A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of the silicon film by processing the silicon film until a part of the second insulating film is exposed by use of etch-back; removing the second insulating film; and performing dry etching by use of a fluorocarbon-based gas, to process the first insulating film by using the sidewall as a mask. The processing of the first insulating film includes applying on the substrate a self-bias voltage Vdc that satisfies a relational expression of Vdc<46x?890, where a film thickness of the silicon film that constitutes the sidewall is x nm (19.5?x?22.1).
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: March 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Hashimoto, Mitsuhiro Omura, Yasuyoshi Hyodo, Takamichi Tsuchiya
  • Publication number: 20110045615
    Abstract: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; and
    Type: Application
    Filed: October 27, 2010
    Publication date: February 24, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiro Omura