Patents by Inventor Mitsuhisa Watanabe

Mitsuhisa Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210225805
    Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
  • Patent number: 10998290
    Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
  • Patent number: 10607966
    Abstract: Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. A first sealing material such as a capillary under fill material is deposited into a first subset of the gaps. A second sealing material such as a mold resin is deposited into a second subset of the gaps. The first and second sealing materials are cured, and the die stacks are then singulated.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mitsuhisa Watanabe
  • Patent number: 10553560
    Abstract: A chip laminate in this semiconductor device has a structure consisting of a first semiconductor chip and a second semiconductor chip laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode formed on one surface and a second bump electrode formed on the other surface. The second semiconductor chip has a circuit-forming layer and a third bump electrode formed on one surface and a fourth bump electrode formed on the other surface. The first semiconductor chip and the second semiconductor chip are laminated together such that the circuit-forming layer on the first semiconductor chip and the circuit-forming layer on the second semiconductor chip face each other and the first and third bump electrodes are electrically connected to each other.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: February 4, 2020
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Mitsuhisa Watanabe
  • Publication number: 20190148338
    Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 16, 2019
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
  • Patent number: 10217719
    Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate formed from a molded material, a first semiconductor die at least partially embedded within the support substrate, a plurality of interconnects extending at least partially through the molded material, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second and third semiconductor dies.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
  • Publication number: 20180366448
    Abstract: Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. A first sealing material such as a capillary under fill material is deposited into a first subset of the gaps. A second sealing material such as a mold resin is deposited into a second subset of the gaps. The first and second sealing materials are cured, and the die stacks are then singulated.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 20, 2018
    Inventor: Mitsuhisa Watanabe
  • Publication number: 20180294249
    Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate formed from a molded material, a first semiconductor die at least partially embedded within the support substrate, a plurality of interconnects extending at least partially through the molded material, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second and third semiconductor dies.
    Type: Application
    Filed: April 6, 2017
    Publication date: October 11, 2018
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
  • Patent number: 10083941
    Abstract: Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. A first sealing material such as a capillary under fill material is deposited into a first subset of the gaps. A second sealing material such as a mold resin is deposited into a second subset of the gaps. The first and second sealing materials are cured, and the die stacks are then singulated.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Mitsuhisa Watanabe
  • Publication number: 20180182738
    Abstract: Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. A first sealing material such as a capillary under fill material is deposited into a first subset of the gaps. A second sealing material such as a mold resin is deposited into a second subset of the gaps. The first and second sealing materials are cured, and the die stacks are then singulated.
    Type: Application
    Filed: February 21, 2018
    Publication date: June 28, 2018
    Inventor: Mitsuhisa Watanabe
  • Patent number: 9935082
    Abstract: Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. A first sealing material such as a capillary under fill material is deposited into a first subset of the gaps. A second sealing material such as a mold resin is deposited into a second subset of the gaps. The first and second sealing materials are cured, and the die stacks are then singulated.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Mitsuhisa Watanabe
  • Publication number: 20170186729
    Abstract: Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. A first sealing material such as a capillary under fill material is deposited into a first subset of the gaps. A second sealing material such as a mold resin is deposited into a second subset of the gaps. The first and second sealing materials are cured, and the die stacks are then singulated.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 29, 2017
    Inventor: Mitsuhisa Watanabe
  • Patent number: 9466546
    Abstract: A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: October 11, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Koichi Hatakeyama, Mitsuhisa Watanabe, Keiyo Kusanagi
  • Publication number: 20160035705
    Abstract: A chip laminate in this semiconductor device has a structure consisting of a first semiconductor chip and a second semiconductor chip laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode formed on one surface and a second bump electrode formed on the other surface. The second semiconductor chip has a circuit-forming layer and a third bump electrode formed on one surface and a fourth bump electrode formed on the other surface. The first semiconductor chip and the second semiconductor chip are laminated together such that the circuit-forming layer on the first semiconductor chip and the circuit-forming layer on the second semiconductor chip face each other and the first and third bump electrodes are electrically connected to each other.
    Type: Application
    Filed: March 18, 2014
    Publication date: February 4, 2016
    Inventor: Mitsuhisa Watanabe
  • Patent number: 9112061
    Abstract: A semiconductor device includes an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer. The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: August 18, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Mitsuhisa Watanabe
  • Patent number: 8816478
    Abstract: Disclosed herein is a device that includes: a semiconductor substrate having a first surface on which a plurality of circuit elements are formed and a second surface opposite to the first surface; an insulating layer covering the second surface of the semiconductor substrate; and a penetration electrode having a body section that penetrates through the semiconductor substrate and a protruding section that is connected to one end of the body section and protrudes from the second surface of the semiconductor substrate. The second surface of the semiconductor substrate is covered with the protruding section of the penetration electrode without intervention of the insulating layer.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: August 26, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Yoshiharu Kanegae, Hisashi Tanie, Mitsuhisa Watanabe, Keiyo Kusanagi
  • Patent number: 8810047
    Abstract: A semiconductor device includes: a substrate having first and second surfaces, the first surface comprising first and second regions; a first semiconductor chip covering the first region; a first seal covering the second region and the first semiconductor chip; and a second seal covering the second surface.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: August 19, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
  • Patent number: 8441126
    Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 ?m or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: May 14, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Ichiro Anjoh
  • Patent number: 8217517
    Abstract: In one embodiment, a semiconductor device includes a printed wiring board provided with a connection pad, a semiconductor chip provided with an electrode pad and a conductive wire. One end of the conductive wire is connected to the connection pad of the printed wiring board and the other end of the conductive wire is connected to the electrode pad of the semiconductor chip. The semiconductor chip is mounted on the printed wiring board so that the first surface of the semiconductor chip provided with the electrode pad is oriented opposite to the printed wiring board. A first insulating layer is formed on the first surface of the semiconductor chip oriented opposite to the printed wiring board. A thermoplastic second insulating layer is formed on the first insulating layer. Part of the conductive wire between one end and the other end is buried in the second insulating layer.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: July 10, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Keiyo Kusanagi
  • Patent number: 8216934
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe