Patents by Inventor Mitsuhisa Watanabe

Mitsuhisa Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8203222
    Abstract: A semiconductor device includes a substrate, a semiconductor chip, and first and second insulations. The substrate has at least a first region and a second region. The semiconductor chip structure covers the first region. The first insulation covers the second region. The first insulation has a first thermal expansion coefficient approximately equal to that of the semiconductor chip structure. The second insulation covers the semiconductor chip structure and the first insulation so that the semiconductor chip structure and the first insulation are sandwiched between the substrate and the second insulation. The second insulation has a second thermal expansion coefficient approximately equal to that of the substrate.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: June 19, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Koichi Hatakeyama, Keiyo Kusanagi
  • Publication number: 20120126402
    Abstract: A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 24, 2012
    Inventors: Koichi HATAKEYAMA, Mitsuhisa Watanabe, Keiyo Kusanagi
  • Publication number: 20120119356
    Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 ?m or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.
    Type: Application
    Filed: May 12, 2011
    Publication date: May 17, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Mitsuhisa WATANABE, Ichiro ANJOH
  • Publication number: 20120118939
    Abstract: The process for manufacturing the semiconductor device and the apparatus, which achieve stable production of semiconductor devices with improved connection reliability, is presented. First terminals of circuit boards 1 are arranged to face the corresponding bumps of semiconductor chips 2, respectively, and the resin layer 3 is disposed between the respective first terminals and the respective bumps to form laminates, and the laminates are simultaneously compressed from a direction of lamination, while heating a plurality of laminates. In such case, the diaphragm 54 disposed in a heating furnace 51 is abutted against a plurality of laminates or a member 531 to elastically deform the members while a plurality of laminates is heated in the heating furnace 51, so that laminates are simultaneously compressed from a direction of lamination, while heating thereof in a vacuum.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 17, 2012
    Applicants: SUMITOMO BAKELITE CO., LTD., ELPIDA MEMORY, INC.
    Inventors: Keiyo KUSANAGI, Koichi HATAKEYAMA, Mitsuhisa WATANABE, Yusuke NAKANOYA, Hidenori MATSUSHITA, Toru MEURA, Kenzou MAEJIMA, Hiroki NIKAIDO, Mina NIKAIDO
  • Patent number: 7993975
    Abstract: A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality of semiconductor chips; preparing a plurality of pre-cut substrates each including a substrate body capable of being cut along corresponding one of cutting lines into a pair of same structured substrate pieces, connection pads provided on a top surface of the substrate body, and external terminals formed on a bottom surface of the substrate body and connected to the connection pads; mounting the pre-cut substrates onto the wafer while the cutting lines of the pre-cut substrates match the dicing lines; and simultaneously dicing the wafer and the pre-cut substrates along the dicing lines matching the cutting lines.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: August 9, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
  • Patent number: 7969019
    Abstract: Semiconductor device 1 includes: first wiring board 5 provided with a plurality of external terminals 9 on the under surface thereof; first semiconductor chip 3 with the under surface thereof mounted on the upper surface of first wiring board 5; and second semiconductor chip 10 with the under surface thereof mounted on the upper surface of first semiconductor chip 3. On the upper surface of first wiring board 5, connecting pad 6a and connecting pad 6b are provided, while connecting pad 6a is electrically connected with the under surface of first semiconductor chip 3 and connecting pad 6b is arranged closely to an end portion of first semiconductor chip 3. Connecting pad 6a and connecting pad 6b are electrically connected with external terminals 9.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: June 28, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Ichiro Anjoh
  • Patent number: 7964962
    Abstract: A method of making a semiconductor apparatus provides a plurality of electrode pads on a main surface of a semiconductor chip, and a plurality of bump electrodes on the electrode pads. The method also provides a wired board which is allocated in a side of the main surface of the chip and is positioned in a central area of the main surface of the chip so as to be separated from an edge part of the chip by at least 50 ?m or more, a plurality of external terminals on the wired board and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and a sealing part between the chip and the wired board, the sealing part being made of underfill material that covers a connection part between the bump electrode and the wiring.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: June 21, 2011
    Assignee: Elpidia Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Ichiro Anjoh
  • Publication number: 20110092065
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Application
    Filed: December 22, 2010
    Publication date: April 21, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Eiji YOSHIDA, Takao OHNO, Yoshito AKUTAGAWA, Koji SAWAHATA, Masataka MIZUKOSHI, Takao NISHIMURA, Akira TAKASHIMA, Mitsuhisa WATANABE
  • Patent number: 7884459
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: February 8, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Publication number: 20110006418
    Abstract: In one embodiment, a semiconductor device includes a printed wiring board provided with a connection pad, a semiconductor chip provided with an electrode pad and a conductive wire. One end of the conductive wire is connected to the connection pad of the printed wiring board and the other end of the conductive wire is connected to the electrode pad of the semiconductor chip. The semiconductor chip is mounted on the printed wiring board so that the first surface of the semiconductor chip provided with the electrode pad is oriented opposite to the printed wiring board. A first insulating layer is formed on the first surface of the semiconductor chip oriented opposite to the printed wiring board. A thermoplastic second insulating layer is formed on the first insulating layer. Part of the conductive wire between one end and the other end is buried in the second insulating layer.
    Type: Application
    Filed: July 6, 2010
    Publication date: January 13, 2011
    Inventors: Mitsuhisa WATANABE, Keiyo KUSANAGI
  • Publication number: 20100301468
    Abstract: A semiconductor device may include, but is not limited to a wiring board, a first insulator, a semiconductor chip, and a second insulator. The first insulator penetrates the wiring board. A top end of the first insulator is higher in level than an upper surface of the wiring board. The semiconductor chip is disposed on the top end of the first insulator. The semiconductor chip is separated from the upper surface of the wiring board. The second insulator covers the semiconductor chip and the upper surface of the wiring board.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 2, 2010
    Inventors: Mitsuhisa WATANABE, Keiyo Kusanagi, Koichi Hatakeyama, Hiroyuki Fujishima
  • Publication number: 20100295167
    Abstract: A semiconductor device includes an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer. The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 25, 2010
    Inventor: Mitsuhisa WATANABE
  • Patent number: 7812439
    Abstract: A semiconductor apparatus includes a semiconductor chip, a wired board, a plurality of bump electrodes, a plurality of external terminals, and insulating material. The semiconductor chip includes a plurality of electrode pads arranged in a central area on one surface. The wired board is arranged as facing one surface of the semiconductor chip, and includes a wiring. The bump electrode is provided between surfaces at which the semiconductor chip and the wired board face each other, and electrically connects the electrode pad and the wiring. The external terminal corresponds to a plurality of bump electrodes, and is mounted on the wired board. The insulating material is provided between the semiconductor chip and the wired board, and covers at least a connection part between the bump electrode and the wiring.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 12, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Ichiro Anjo
  • Publication number: 20100252923
    Abstract: A semiconductor device of the present invention includes a semiconductor chip formed with an electrode pad on a front side thereof, a wiring board having a wiring pattern, the wiring board having a front side opposing the back side of the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, an external terminal arranged on the back side of the wiring board for electrical connection with the electrode pad through the wire and the wiring pattern, and a sealant for fixing the semiconductor chip on the front side of the wiring board so as to form a hollow which is continuous to a portion straddling the entirety of the back side of the semiconductor chip and the front side of the wiring board, and continuous to a portion adjacent to at least one outer peripheral surface of the semiconductor chip except for the back side of the same. The wiring board includes a throughhole in communication with the hollow.
    Type: Application
    Filed: March 18, 2010
    Publication date: October 7, 2010
    Inventors: Mitsuhisa WATANABE, Keiyo Kusanagi, Koichi Hatakeyama
  • Patent number: 7786564
    Abstract: A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: August 31, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Ichiro Anjoh
  • Publication number: 20100148172
    Abstract: A semiconductor device includes: a semiconductor chip; a plurality of electrode pads on the semiconductor chip; a wiring board fixed to the semiconductor chip; a plurality of connection pads on the wiring board; a plurality of bonding pads aligned along two sides of the wiring board; and a plurality of leads on the wiring board. The plurality of electrode pads is in a center region of the semiconductor chip. The plurality of second connection pads faces the plurality of electrode pads. The plurality of leads connects the plurality of connection pads to the plurality of bonding pads.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 17, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuhisa Watanabe, Keiyo Kusanagi
  • Publication number: 20100133722
    Abstract: A method for a semiconductor device includes the following processes. A first seal layer is formed in a cavity of a first mold, the first seal layer being in a liquid state. A second seal layer is formed over the first seal layer while the first seal layer is kept in the liquid state, and the second seal layer is in a liquid state. A semiconductor chip on a wiring board fixed on a second mold is immersed into the second seal layer. The first and second seal layers are thermally cured.
    Type: Application
    Filed: November 20, 2009
    Publication date: June 3, 2010
    Applicant: Elpida Memory, Inc
    Inventor: Mitsuhisa Watanabe
  • Publication number: 20100102438
    Abstract: A semiconductor device includes: a substrate having first and second surfaces, the first surface comprising first and second regions; a first semiconductor chip covering the first region; a first seal covering the second region and the first semiconductor chip; and a second seal covering the second surface.
    Type: Application
    Filed: October 13, 2009
    Publication date: April 29, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
  • Publication number: 20090321912
    Abstract: A semiconductor device includes a substrate, a semiconductor chip, and first and second insulations. The substrate has at least a first region and a second region. The semiconductor chip structure covers the first region. The first insulation covers the second region. The first insulation has a first thermal expansion coefficient approximately equal to that of the semiconductor chip structure. The second insulation covers the semiconductor chip structure and the first insulation so that the semiconductor chip structure and the first insulation are sandwiched between the substrate and the second insulation. The second insulation has a second thermal expansion coefficient approximately equal to that of the substrate.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 31, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuhisa Watanabe, Koichi Hatakeyama, Keiyo Kusanagi
  • Patent number: 7571538
    Abstract: The present invention relates to a Jig and method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: August 11, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka