Abstract: A three-dimensional stacked structured semiconductor device comprising semiconductor circuit layers stacked on a support substrate, and a method of fabricating the device are provided. After fixing semiconductor chips 37 to a support substrate 31 with bump electrodes, gaps between the chips 37 are filled with an electrically insulative adhesive 38. Then, by polishing the reverses of the chips 37, the chips 37 are thinned to expose buried interconnections in the chips 37, thereby forming a first semiconductor circuit layer L1. Next, after fixing semiconductor chips 43 to the first semiconductor circuit layer L1 with bump electrodes 41 and 42 by way of an insulating layer 39, gaps between the chips 43 are filled with an electrically insulative adhesive 44. Then, by polishing the reverses of the chips 43, the chips 43 are thinned to expose buried interconnections in the chips 43, thereby forming a second semiconductor circuit layer L2.

Abstract: In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of water films 81. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.

Abstract: A nonvolatile semiconductor memory element enabling to improve insulation performance of an insulator around a floating gate and to decrease the ratio of oxidized metal ultrafine particles in the floating gate, are provided. In a process for producing nonvolatile semiconductor memory element comprising a floating gate made of a hardly oxidizable material having a Gibbs' formation free energy for forming its oxide higher than that of Si in a range of from 0° C. to 1,200° C.

Abstract: A nonvolatile semiconductor memory device including a source region and a drain region formed on a surface of a semiconductor substrate, a channel-forming region formed so as to connect the source region and the drain region or so as to be sandwiched between the source region and the drain region, a tunnel insulating film formed in contact with the channel-forming region, a charge retention layer formed adjacently to the tunnel insulating film, a gate insulating film formed adjacently to the charge retention layer, and a control gate formed adjacently to the gate insulating film. The charge retention layer includes an insulating matrix having, per nonvolatile semiconductor memory device, one conductive nano-particle which is made of at least one single-element substance or chemical compound that functions as a floating gate.

Abstract: The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.

Abstract: A nickel-silicon compound forming method is disclosed which comprises forming nickel on at least one of only silicon and a compound containing silicon, and performing stepwise-heating of the nickel together with the at least one of only silicon and the compound containing silicon.

Abstract: A solid-state image sensor has a chip-size package, which can be easily fabricated. The element-formation regions are formed in the semiconductor substrate (21) of the light-receiving element layer (20) corresponding to the pixel regions. The semiconductor light-receiving elements (PD) are formed in the respective element-formation regions and covered with the light-transmissive insulator films (25a), (25b) and (26). The light-introducing layer (40), which includes the light-introducing cavity (42) and the quartz cap (51) for closing the cavity, is formed on the film (26). The microlenses (43) are incorporated into the cavity (42). The electric output signals of the semiconductor light-receiving elements (PD) are taken out to the bottom of the substrate (21) by way of the buried interconnections of the substrate (21) and then, derived to the outside of the image sensor by way of the output layer (10) or the interposer (10A).

Abstract: There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used.

Abstract: The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.

Abstract: There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used.

Abstract: The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.

Abstract: There is disclosed a method of forming a nickel film on a silicon substrate or a silicon film, followed by applying an annealing process such that a final annealing temperature TH is in the range of 500° C.<TH?600° C. to form a nickel-silicon compound, the method comprising a first annealing step of, by using an annealing device configured to change an annealing temperature in a stepwise manner, heating the substrate up to a first annealing temperature close to 400° C., followed by annealing the substrate at the first annealing temperature for a predetermined period, and a second annealing step of, by using the annealing device, heating the substrate up to a second annealing temperature which is the final annealing temperature TH, followed by annealing the substrate at the second annealing temperature for a predetermined period.

Abstract: A nickel-silicon compound forming method is disclosed which comprises forming nickel on at least one of only silicon and a compound containing silicon, and performing stepwise-heating of the nickel together with the at least one of only silicon and the compound containing silicon.

Abstract: There is provided a nonvolatile semiconductor memory device which can shorten data writing and erasing time, significantly improve the endurance characteristic and be activated with low power consumption. The nonvolatile semiconductor memory device comprises an insulating layer 3b with electric insulation, wherein, a charge retention layer 3 formed adjacent to a tunnel insulating film 2 contains nano-particles 3a comprised of a compound which is constituted from at least one single-element substance or chemical compound having a particle diameter of at most 5 nm functions as a floating gate, and which are independently dispersed with a density of from 10+12 to 10+14 particles per square centimeter.

Abstract: A solid-state image sensor has a chip-size package, which can be easily fabricated. The element-formation regions are formed in the semiconductor substrate (21) of the light-receiving element layer (20) corresponding to the pixel regions. The semiconductor light-receiving elements (PD) are formed in the respective element-formation regions and covered with the light-transmissive insulator films (25a), (25b) and (26). The light-introducing layer (40), which includes the light-introducing cavity (42) and the quartz cap (51) for closing the cavity, is formed on the film (26). The microlenses (43) are incorporated into the cavity (42). The electric output signals of the semiconductor light-receiving elements (PD) are taken out to the bottom of the substrate (21) by way of the buried interconnections of the substrate (21) and then, derived to the outside of the image sensor by way of the output layer (10) or the interposer (10A).

Abstract: The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.

Abstract: A nickel-silicon compound forming method is disclosed which comprises forming nickel on at least one of only silicon and a compound containing silicon, and performing stepwise-heating of the nickel together with the at least one of only silicon and the compound containing silicon.

Abstract: A three-dimensional semiconductor integrated circuit apparatus which permits ready electrical connection and is resistant to deformation and easy to fabricate and a manufacturing method therefor are provided. A second semiconductor substrate is stacked over a third semiconductor substrate, and a first semiconductor substrate is stacked over the second semiconductor substrate. A second integrated circuit is formed over the surface layer of the second semiconductor substrate, and the integrated circuit side of the second semiconductor substrate is bonded to the integrated circuit side of the first semiconductor substrate, resulting in the electrical connection of the first integrated circuit formed over the surface layer of the first semiconductor substrate and the second integrated circuit.

Abstract: A three-dimensional semiconductor integrated circuit apparatus which permits ready electrical connection and is resistant to deformation and easy to fabricate and a manufacturing method therefor are provided. A second semiconductor substrate is stacked over a third semiconductor substrate, and a first semiconductor substrate is stacked over the second semiconductor substrate. A second integrated circuit is formed over the surface layer of the second semiconductor substrate, and the integrated circuit side of the second semiconductor substrate is bonded to the integrated circuit side of the first semiconductor substrate, resulting in the electrical connection of the first integrated circuit formed over the surface layer of the first semiconductor substrate and the second integrated circuit.

Abstract: A ring bus multiprocessor system whose processors are laid out and connected in such a manner that the system is enhanced in stability and performance, is easy to modify in scale, and is lowered in manufacturing cost. On a processor board, processors are serially connected by communication buses to form a processor group. Each processor board may have an even-numbered plurality of processor groups mounted thereon. A plurality of processor boards are laid out in parallel and are interconnected between adjacent boards by means of inter-processor communication buses. Each of the odd-numbered processor groups is connected from one board to the next up to the most downstream board where the connection is looped back to the adjacent even-numbered processor group. In turn, the even-numbered processor group is connected from one board to the next back to the most upstream board where the connection is again looped back to the adjacent odd-numbered processor group, and so on, whereby a ring bus arrangement is formed.