Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A DRAM having the capacitors of memory cells formed by utilizing moats is disclosed. The moats are provided in a semiconductor substrate independently for the respective capacitors by anistropic dry etching, and they serve to increase the capacitances of the capacitors without increasing the areas which they occupy. The greater part of each capacitor is buried in the moat. The capacitors are electrically isolated from the semiconductor substrate, and the semiconductor substrate is not used as the electrodes of the capacitors. The capacitor consists of first and second polycrystalline silicon layers, and an insulator film formed therebetween. The first polycrystalline silicon layer serves as a lower electrode electrically isolated from the semiconductor substrate. This first polycrystalline silicon layer is formed independently for each capacitor, and it is connected to the source or drain region of the MISFET of the memory cell.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A process for fabricating a semiconductor device having n-channel and p-channel MOSFET's. Each MOSFET has a pair of side walls that are simultaneously formed on both sides of the gate electrode. The n-channel MOSFET has source and drain regions consisting of a low-concentration region formed by implanting ions using the gate electrode as a mask, and a high-concentration region formed by implanting ions using the gate electrode and side walls as masks. The p-channel MOSFET has source and drain regions consisting of high-concentration regions formed by implanting ions using the gate electrode and side walls as masks.

Abstract: A silicide layer of a refractory metal for reducing resistance and a nitride layer for preventing diffusion of aluminum are formed on the source and drain regions of an MISFET. The silicide layer is formed in self-alignment with the source and drain regions by two annealings effected at a low temperature and at a high temperature, respectively, and has a low resistance. The nitride layer is formed by directly nitriding the silicide layer.

Abstract: A semiconductor memory comprising a memory cell disposed on a p-type semiconductor substrate and including an insulated-gate field effect transistor and a storage capacitor. The storage capacitor comprises: an insulator capacitor including a first electrode disposed on the substrate, a film of Si.sub.3 N.sub.4 disposed on the first electrode, and a second electrode disposed on the Si.sub.3 N.sub.4 film; and a pn junction capacitor including a first n-type impurity region for constituting either the source or drain of the insulated-gate field effect transistor, and a second p-type impurity region disposed in contact with the first impurity region and having a higher impurity concentration than the substrate.

Abstract: A semiconductor memory device consisting of a storage capacitance and an insulated gate field-effect transistor, wherein over a first conductive substance which lies in contact with a source of drain region constituting the transistor and which becomes a gate of the transistor through a first insulating film, a second conductive substance is deposited so that at least a part thereof may be stacked over the first conductive substance, and wherein a second insulating film and a third conductive substance are successively deposited on the second conductive substance, whereby the second conductive substance, the second insulating film and the third conductive substance constitute the storge capacitance.

Abstract: A polycrystalline silicon layer is deposited by chemical vapor deposition method at a predetermined location on an oxide film grown by thermal oxidation on a surface of a monocrystal silicon substrate. Nitrogen ions are implanted in the outer surface of the polycrystalline silicon layer and the exposed surface of the oxide film. The whole surfaces are oxidized by wet oxidation so as to form a thick oxide layer at the surface of the oxide film which is not covered by the polycrystalline silicon layer.