Patents by Inventor Mitsuo Morooka

Mitsuo Morooka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9716251
    Abstract: A display device includes light emitting elements that are arranged in a two-dimensional matrix, in which the light emitting elements include a drive circuit which is provided on a substrate, a first insulating layer which covers the drive circuit and the substrate, a light emitting portion in which a first electrode, an organic layer having a light emitting layer, and a second electrode are laminated, and a second insulating layer which covers the first electrode.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 25, 2017
    Assignee: SONY CORPORATION
    Inventors: Masanao Uesugi, Jiro Yamada, Mitsuo Morooka, Yasunobu Hiromasu
  • Publication number: 20160020433
    Abstract: A display device includes light emitting elements that are arranged in a two-dimensional matrix, in which the light emitting elements include a drive circuit which is provided on a substrate, a first insulating layer which covers the drive circuit and the substrate, a light emitting portion in which a first electrode, an organic layer having a light emitting layer, and a second electrode are laminated, and a second insulating layer which covers the first electrode.
    Type: Application
    Filed: September 24, 2015
    Publication date: January 21, 2016
    Inventors: Masanao Uesugi, Jiro Yamada, Mitsuo Morooka, Yasunobu Hiromasu
  • Patent number: 9178174
    Abstract: A display device includes light emitting elements that are arranged in a two-dimensional matrix, in which the light emitting elements include a drive circuit which is provided on a substrate, a first insulating layer which covers the drive circuit and the substrate, a light emitting portion in which a first electrode, an organic layer having a light emitting layer, and a second electrode are laminated, and a second insulating layer which covers the first electrode.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: November 3, 2015
    Assignee: SONY CORPORATION
    Inventors: Masanao Uesugi, Jiro Yamada, Mitsuo Morooka, Yasunobu Hiromasu
  • Publication number: 20130256638
    Abstract: A display device includes light emitting elements that are arranged in a two-dimensional matrix, in which the light emitting elements include a drive circuit which is provided on a substrate, a first insulating layer which covers the drive circuit and the substrate, a light emitting portion in which a first electrode, an organic layer having a light emitting layer, and a second electrode are laminated, and a second insulating layer which covers the first electrode.
    Type: Application
    Filed: March 19, 2013
    Publication date: October 3, 2013
    Applicant: Sony Corporation
    Inventors: Masanao Uesugi, Jiro Yamada, Mitsuo Morooka, Yasunobu Hiromasu
  • Publication number: 20120241733
    Abstract: Disclosed herein is a display device including a semiconductor layer, a gate electrode, a source/drain electrode layer, and an organic electric field light-emitting element. The semiconductor layer is provided on a substrate and made of an oxide semiconductor. The gate electrode is provided above a selective first region of the semiconductor layer with a gate insulating film sandwiched therebetween. The source/drain electrode layer is adapted to serve as a source or drain and electrically connected to a second region of the semiconductor layer adjacent to the first region thereof. Also, the organic electric field light-emitting element is provided above a third region of the semiconductor layer different from the first and second region thereof, the organic electric field light-emitting element having a region for the third region that is driven as a pixel electrode.
    Type: Application
    Filed: March 12, 2012
    Publication date: September 27, 2012
    Applicant: Sony Corporation
    Inventors: Mitsuo Morooka, Yasunobu Hiromasu
  • Patent number: 7719184
    Abstract: Provided is an organic EL element including: a first electrode 13; a protection layer 15 that is formed on the first electrode 13 and has an opening portion through which the first electrode 13 is exposed; an insulation layer 17 that is formed on the protection layer 15; an organic layer 19 that is formed over the insulation layer 17 and the first electrode 13 exposed through the opening portion, and includes an emission layer; and a second electrode 21 formed on the organic layer 19, wherein a film thickness of the protection layer 15 is less than that of the organic layer 19.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: May 18, 2010
    Assignee: Kyocera Corporation
    Inventors: Keigo Kanoh, Mitsuo Morooka, Taro Hasumi, Hiromi Fukuoka, Masaya Watanabe
  • Patent number: 7592275
    Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: September 22, 2009
    Assignee: Au Optronics Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Patent number: 7569858
    Abstract: A thin film transistor according to the present invention includes a gate electrode, a semiconductor layer having a channel forming region arranged on the gate electrode and an impurity region arranged on a part of the channel forming region, source and drain electrodes electrically connected to the impurity region, and a gate insulating film that electrically insulates the gate electrode and the semiconductor layer, wherein the distance between the upper end of the gate electrode and the upper end of the impurity region is larger than the distance between the upper end of the gate electrode and the upper end of the channel forming region.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: August 4, 2009
    Assignee: Kyocera Corporation
    Inventors: Takatoshi Tsujimura, Shinya Ono, Mitsuo Morooka, Koichi Miwa
  • Publication number: 20080230007
    Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.
    Type: Application
    Filed: November 14, 2007
    Publication date: September 25, 2008
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Patent number: 7344927
    Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: March 18, 2008
    Assignee: Au Optronics Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Publication number: 20070176545
    Abstract: Provided is an organic EL element including: a first electrode 13; a protection layer 15 that is formed on the first electrode 13 and has an opening portion through which the first electrode 13 is exposed; an insulation layer 17 that is formed on the protection layer 15; an organic layer 19 that is formed over the insulation layer 17 and the first electrode 13 exposed through the opening portion, and includes an emission layer; and a second electrode 21 formed on the organic layer 19, wherein a film thickness of the protection layer 15 is less than that of the organic layer 19.
    Type: Application
    Filed: July 28, 2006
    Publication date: August 2, 2007
    Applicant: Kyocera Corporation
    Inventors: Keigo Kanoh, Mitsuo Morooka, Taro Hasumi, Hiromi Fukuoka, Masaya Watanabe
  • Patent number: 7221089
    Abstract: An organic light emitting diode display device includes a plurality of organic light emitting diode elements that are arranged in a matrix; a plurality of protective layers, each of the protective layers covering at least one of the organic light emitting diode elements; and a stress relaxation layer that is formed between the protective layers, for relaxing a stress caused by the protective layers. The stress relaxation layer may surround the protective layer. Moreover, the stress relaxation layer may be made of a shading material, and serve as a mask for forming the organic light emitting diode elements.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: May 22, 2007
    Assignees: Chi Mei Optoelectronics Corp., Kyocera Corporation
    Inventors: Takatoshi Tsujimura, Mitsuo Morooka, Kuniaki Sueoka, Sayuri Kohara
  • Patent number: 7173278
    Abstract: A thin film transistor according to the present invention includes a gate electrode, a semiconductor layer having a channel forming region arranged on the gate electrode and an impurity region arranged on a part of the channel forming region, source and drain electrodes electrically connected to the impurity region, and a gate insulating film that electrically insulates the gate electrode and the semiconductor layer, wherein the distance between the upper end of the gate electrode and the upper end of the impurity region is larger than the distance between the upper end of the gate electrode and the upper end of the channel forming region.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: February 6, 2007
    Assignee: Kyocera Corporation
    Inventors: Takatoshi Tsujimura, Shinya Ono, Mitsuo Morooka, Koichi Miwa
  • Publication number: 20070007528
    Abstract: A thin film transistor according to the present invention includes a gate electrode, a semiconductor layer having a channel forming region arranged on the gate electrode and an impurity region arranged on a part of the channel forming region, source and drain electrodes electrically connected to the impurity region, and a gate insulating film that electrically insulates the gate electrode and the semiconductor layer, wherein the distance between the upper end of the gate electrode and the upper end of the impurity region is larger than the distance between the upper end of the gate electrode and the upper end of the channel forming region.
    Type: Application
    Filed: September 11, 2006
    Publication date: January 11, 2007
    Inventors: Takatoshi Tsujimura, Shinya Ono, Mitsuo Morooka, Koichi Miwa
  • Patent number: 7122956
    Abstract: An organic light emitting diode (OLED) display comprises: an insulating substrate; common electrodes; a first electrode layer formed in a region adjacent to the common electrodes formed on the insulating substrate electrically isolated from the common electrodes; an insulating layer which coats the insulating substrate and respectively opens a first opening window exposing a part of the common electrodes and a second opening window exposing at least a part of the first electrode layer; ribs or walls which form a cell area by crossing the common electrodes on the insulating substrate and surround each of the opening windows; a material layer formed on the first electrode layer exposed by the second opening window; and a second electrode layer which coats the cell area surrounded by the ribs and is electrically connected to the common electrodes through the first opening window.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: October 17, 2006
    Assignees: Chi Mei Optoelectronics Corp., Kyocera Corporation
    Inventors: Nami Ikeda, Mitsuo Morooka, Shinya Ono, Keigo Kanoh, Koji Murayama, Koichi Miwa
  • Patent number: 7115448
    Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: October 3, 2006
    Assignee: AU Optronics Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Patent number: 7091940
    Abstract: A technique to reduce the rate of increase in threshold voltage, i.e. degradation, of an amorphous silicon TFT driving an OLED. A first supply voltage is supplied to a drain of the TFT when a first control voltage is applied to a gate of the TFT to activate the TFT and drive the OLED. However, a second, lower supply voltage is supplied to the drain of the TFT when a second control voltage is applied to the gate of the TFT to deactivate the TFT and turn off the OLED, whereby a voltage differential between the drain and the source when the second control voltage is applied to the gate is substantially lower said first supply voltage. This reduces degradation of the TFT. According to one feature of the present invention, when the TFT is turned off by the absence of voltage applied to its gate, the voltage at the drain of the TFT is reduced to approximately zero to minimize the voltage differential between the drain and the source.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: August 15, 2006
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Takatoshi Tsujimura, Kohichi Miwa, Mitsuo Morooka
  • Publication number: 20060145163
    Abstract: An organic light emitting diode device of the present invention comprises a substrate, a light-transmissive electrode formed on the substrate, a coating-film-formative function layer including a hole transport material and an electron transport material, the function layer being formed on the substrate, trench patterns formed on the function layer, dopant doped into the function layer between walls forming these trench patterns, and a light-reflective electrode coating the trench patterns. The dopant is introduced into the trench patterns by a capillary phenomenon, thus enabling high-definition color patterning. Moreover, the present invention provides a method for manufacturing the above-described organic light emitting diode device.
    Type: Application
    Filed: September 12, 2003
    Publication date: July 6, 2006
    Inventors: Takatoshi Tsujimura, Mitsuo Morooka, Kelgo Kanoh, Kohichi Miwa
  • Patent number: 7038278
    Abstract: A thin film transistor is circular when viewed from top. A first source/drain region is disposed at the center, a semiconductor layer surrounds the first source/drain region and overlaps with an external periphery of the first source/drain region, and a second source/drain region surrounds the semiconductor layer and overlaps the external periphery of the semiconductor layer. The potential of the second source/drain region is set higher than the potential of the first source/drain region. The external periphery of the first source/drain region and the internal periphery of the second source/drain region have concentric circular shapes.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 2, 2006
    Assignees: Chi-Mei Optoelectronics Corp., Kyocera Corporation
    Inventors: Takatoshi Tsujimura, Mitsuo Morooka
  • Publication number: 20050258745
    Abstract: An organic light emitting diode display device includes a plurality of organic light emitting diode elements that are arranged in a matrix; a plurality of protective layers, each of the protective layers covering at least one of the organic light emitting diode elements; and a stress relaxation layer that is formed between the protective layers, for relaxing a stress caused by the protective layers. The stress relaxation layer may surround the protective layer. Moreover, the stress relaxation layer may be made of a shading material, and serve as a mask for forming the organic light emitting diode elements.
    Type: Application
    Filed: September 2, 2003
    Publication date: November 24, 2005
    Inventors: Takatoshi Tsujimura, Mitsuo Morooka, Kuniaki Sueoka, Sayuri Kohara