Patents by Inventor Mitsuo Morooka

Mitsuo Morooka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6859252
    Abstract: An active matrix substrate includes a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, which are sequentially deposited on an insulating substrate. A transparent conductive layer is deposited on the source and drain electrodes so that the transparent conductive layer includes a portion deposited to be substantially the same pattern as those of the source and drain electrodes. The transparent conductive layer is connected to either the source electrode or the drain electrode to form a pixel electrode. A gate line is further included on which the gate insulating film is deposited. The gate line is to be connected to the gate electrode.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: February 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Kohichi Miwa, Mitsuo Morooka
  • Publication number: 20040262607
    Abstract: A thin film transistor according to the present invention includes a gate electrode, a semiconductor layer having a channel forming region arranged on the gate electrode and an impurity region arranged on a part of the channel forming region, source and drain electrodes electrically connected to the impurity region, and a gate insulating film that electrically insulates the gate electrode and the semiconductor layer, wherein the distance between the upper end of the gate electrode and the upper end of the impurity region is larger than the distance between the upper end of the gate electrode and the upper end of the channel forming region.
    Type: Application
    Filed: May 12, 2004
    Publication date: December 30, 2004
    Inventors: Takatoshi Tsujimura, Shinya Ono, Mitsuo Morooka, Koichi Miwa
  • Patent number: 6816209
    Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leak current from another data line. More particularly, the present invention is directed to a thin film transistor comprising a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk running from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Takashi Miyamoto, Osamu Tokuhiro, Mitsuo Morooka
  • Publication number: 20040203195
    Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
    Type: Application
    Filed: April 28, 2004
    Publication date: October 14, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Patent number: 6801266
    Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leakage current from another signal line. A thin film transistor comprises a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer 27 formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk leakage current flowing from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: October 5, 2004
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Takashi Miyamoto, Osamu Tokuhiro, Mitsuo Morooka
  • Publication number: 20040165121
    Abstract: An active matrix substrate includes a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, which are sequentially deposited on an insulating substrate. A transparent conductive layer is deposited on the source and drain electrodes so that the transparent conductive layer includes a portion deposited to be substantially the same pattern as those of the source and drain electrodes. The transparent conductive layer is connected to either the source electrode or the drain electrode to form a pixel electrode. A gate line is further included on which the gate insulating film is deposited. The gate line is to be connected to the gate electrode.
    Type: Application
    Filed: February 24, 2004
    Publication date: August 26, 2004
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Kohichi Miwa, Mitsuo Morooka
  • Patent number: 6753550
    Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: June 22, 2004
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Publication number: 20040105041
    Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leak current from another data line.
    Type: Application
    Filed: July 11, 2003
    Publication date: June 3, 2004
    Applicant: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Takashi Miyamoto, Osamu Tokuhiro, Mitsuo Morooka
  • Patent number: 6727645
    Abstract: An organic LED device comprises a substrate, a first driver TFT on the substrate, a second driver TFT on said substrate, and an insulating film on the substrate, the first driver TFT and the second driver TFT. There is a common anode on the insulating film. A first organic LED element is on a first portion of the anode and configured as a top emission struction, and a second organic LED element is on a second portion of the anode and configured as a top emission structure. A first cathode extends into the insulating film and electrically connects the first LED element with the first driver TFT. A second cathode extends into the insulating film and electrically connects the second LED element with the second driver TFT.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: April 27, 2004
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Atsushi Tanaka, Kohichi Miwa, Mitsuo Morooka
  • Patent number: 6707513
    Abstract: An active matrix substrate includes a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, which are sequentially deposited on an insulating substrate. A transparent conductive layer is deposited on the source and drain electrodes so that the transparent conductive layer includes a portion deposited to be substantially the same pattern as those of the source and drain electrodes. The transparent conductive layer is connected to either the source electrode or the drain electrode to form a pixel electrode. A gate line is further included on which the gate insulating film is deposited. The gate line is to be connected to the gate electrode.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: March 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Kohichi Miwa, Mitsuo Morooka
  • Publication number: 20040036072
    Abstract: A thin film transistor is circular when viewed from top. A first source/drain region is disposed at the center, a semiconductor layer surrounds the first source/drain region and overlaps with an external periphery of the first source/drain region, and a second source/drain region surrounds the semiconductor layer and overlaps the external periphery of the semiconductor layer. The potential of the second source/drain region is set higher than the potential of the first source/drain region. The external periphery of the first source/drain region and the internal periphery of the second source/drain region have concentric circular shapes.
    Type: Application
    Filed: August 12, 2003
    Publication date: February 26, 2004
    Applicant: CHI MEI OPTOELECTRONICS CORP.
    Inventors: Takatoshi Tsujimura, Mitsuo Morooka
  • Publication number: 20040001037
    Abstract: A technique to reduce the rate of increase in threshold voltage, i.e. degradation, of an amorphous silicon TFT driving an OLED. A first supply voltage is supplied to a drain of the TFT when a first control voltage is applied to a gate of the TFT to activate the TFT and drive the OLED. However, a second, lower supply voltage is supplied to the drain of the TFT when a second control voltage is applied to the gate of the TFT to deactivate the TFT and turn off the OLED, whereby a voltage differential between the drain and the source when the second control voltage is applied to the gate is substantially lower said first supply voltage. This reduces degradation of the TFT. According to one feature of the present invention, when the TFT is turned off by the absence of voltage applied to its gate, the voltage at the drain of the TFT is reduced to approximately zero to minimize the voltage differential between the drain and the source.
    Type: Application
    Filed: March 20, 2003
    Publication date: January 1, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takatoshi Tsujimura, Kohichi Miwa, Mitsuo Morooka
  • Patent number: 6653178
    Abstract: A thin film transistor and method of making the same is disclosed in which a contact hole is formed with a flattened interface between openings in an inorganic material passivation layer and an organic material interlayer insulating film thereabove. The method includes etching an opening in the interlayer insulating film, using that opening as a mask for subsequently etching a self-aligned opening in the passivation layer, and again etching the interlayer insulating film in a develop back process to obtain a contact hole having a flattened inner sidewall.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: November 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Taroh Hasumi, Osamu Tokuhiro, Mitsuo Morooka
  • Publication number: 20030146711
    Abstract: An organic LED device comprises a substrate, a first driver TFT on the substrate, a second driver TFT on said substrate, and an insulating film on the substrate, the first driver TFT and the second driver TFT. There is a common anode on the insulating film. A first organic LED element is on a first portion of the anode and configured as a top emission struction, and a second organic LED element is on a second portion of the anode and configured as a top emission structure. A first cathode extends into the insulating film and electrically connects the first LED element with the first driver TFT. A second cathode extends into the insulating film and electrically connects the second LED element with the second driver TFT.
    Type: Application
    Filed: January 23, 2003
    Publication date: August 7, 2003
    Inventors: Takatoshi Tsujimura, Atsushi Tanaka, Kohichi Miwa, Mitsuo Morooka
  • Patent number: 6600196
    Abstract: The present invention relates to minimizing a leakage current in a floating island portion formed in a thin film transistor. More specifically, the present invention is directed to a thin film transistor including: a source electrode 14 and a drain electrode 15 disposed above an insulating substrate 11 at a predetermined interval; an s-Si film 16 disposed in relation to the source electrode 14 and drain electrode 15; a gate insulating film 17 overlapping the a-Si film 16; and a gate electrode 18 overlapping the gate insulating film 17, in which the a-Si film 16 is disposed between the source electrode 14 and the drain electrode 15 and has a floating island portion 20 above which or beneath which the gate electrode 18 is not formed, and boron ions are implanted into this portion to form a boron-ion-implanted region 19.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Publication number: 20030122126
    Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 3, 2003
    Applicant: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Patent number: 6525341
    Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: February 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Publication number: 20020106839
    Abstract: A thin film transistor and method of making the same is disclosed in which a contact hole is formed with a flattened interface between openings in an inorganic material passivation layer and an organic material interlayer insulating film thereabove. The method includes etching an opening in the interlayer insulating film, using that opening as a mask for subsequently etching a self-aligned opening in the passivation layer, and again etching the interlayer insulating film in a develop back process to obtain a contact hole having a flattened inner sidewall.
    Type: Application
    Filed: January 31, 2002
    Publication date: August 8, 2002
    Applicant: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Taroh Hasumi, Osamu Tokuhiro, Mitsuo Morooka
  • Publication number: 20020016026
    Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.
    Type: Application
    Filed: May 15, 2001
    Publication date: February 7, 2002
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Publication number: 20020003587
    Abstract: An active matrix substrate includes a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, which are sequentially deposited on an insulating substrate. A transparent conductive layer is deposited on the source and drain electrodes so that the transparent conductive layer includes a portion deposited to be substantially the same pattern as those of the source and drain electrodes. The transparent conductive layer is connected to either the source electrode or the drain electrode to form a pixel electrode. A gate line is further included on which the gate insulating film is deposited. The gate line is to be connected to the gate electrode.
    Type: Application
    Filed: July 6, 2001
    Publication date: January 10, 2002
    Applicant: IBM
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Kohichi Miwa, Mitsuo Morooka