Patents by Inventor Mitsuo Morooka
Mitsuo Morooka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6859252Abstract: An active matrix substrate includes a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, which are sequentially deposited on an insulating substrate. A transparent conductive layer is deposited on the source and drain electrodes so that the transparent conductive layer includes a portion deposited to be substantially the same pattern as those of the source and drain electrodes. The transparent conductive layer is connected to either the source electrode or the drain electrode to form a pixel electrode. A gate line is further included on which the gate insulating film is deposited. The gate line is to be connected to the gate electrode.Type: GrantFiled: February 24, 2004Date of Patent: February 22, 2005Assignee: International Business Machines CorporationInventors: Takatoshi Tsujimura, Osamu Tokuhiro, Kohichi Miwa, Mitsuo Morooka
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Publication number: 20040262607Abstract: A thin film transistor according to the present invention includes a gate electrode, a semiconductor layer having a channel forming region arranged on the gate electrode and an impurity region arranged on a part of the channel forming region, source and drain electrodes electrically connected to the impurity region, and a gate insulating film that electrically insulates the gate electrode and the semiconductor layer, wherein the distance between the upper end of the gate electrode and the upper end of the impurity region is larger than the distance between the upper end of the gate electrode and the upper end of the channel forming region.Type: ApplicationFiled: May 12, 2004Publication date: December 30, 2004Inventors: Takatoshi Tsujimura, Shinya Ono, Mitsuo Morooka, Koichi Miwa
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Thin film transistor, liquid crystal display panel, and method of manufacturing thin film transistor
Patent number: 6816209Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leak current from another data line. More particularly, the present invention is directed to a thin film transistor comprising a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk running from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.Type: GrantFiled: July 11, 2003Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Takatoshi Tsujimura, Takashi Miyamoto, Osamu Tokuhiro, Mitsuo Morooka -
Publication number: 20040203195Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.Type: ApplicationFiled: April 28, 2004Publication date: October 14, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
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Thin film transistor, liquid crystal display panel, and method of manufacturing thin film transistor
Patent number: 6801266Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leakage current from another signal line. A thin film transistor comprises a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer 27 formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk leakage current flowing from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.Type: GrantFiled: July 12, 2000Date of Patent: October 5, 2004Assignee: International Business Machines CorporationInventors: Takatoshi Tsujimura, Takashi Miyamoto, Osamu Tokuhiro, Mitsuo Morooka -
Publication number: 20040165121Abstract: An active matrix substrate includes a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, which are sequentially deposited on an insulating substrate. A transparent conductive layer is deposited on the source and drain electrodes so that the transparent conductive layer includes a portion deposited to be substantially the same pattern as those of the source and drain electrodes. The transparent conductive layer is connected to either the source electrode or the drain electrode to form a pixel electrode. A gate line is further included on which the gate insulating film is deposited. The gate line is to be connected to the gate electrode.Type: ApplicationFiled: February 24, 2004Publication date: August 26, 2004Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Kohichi Miwa, Mitsuo Morooka
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Patent number: 6753550Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.Type: GrantFiled: December 30, 2002Date of Patent: June 22, 2004Assignee: International Business Machines CorporationInventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
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Thin film transistor, liquid crystal display panel, and method of manufacturing thin film transistor
Publication number: 20040105041Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leak current from another data line.Type: ApplicationFiled: July 11, 2003Publication date: June 3, 2004Applicant: International Business Machines CorporationInventors: Takatoshi Tsujimura, Takashi Miyamoto, Osamu Tokuhiro, Mitsuo Morooka -
Patent number: 6727645Abstract: An organic LED device comprises a substrate, a first driver TFT on the substrate, a second driver TFT on said substrate, and an insulating film on the substrate, the first driver TFT and the second driver TFT. There is a common anode on the insulating film. A first organic LED element is on a first portion of the anode and configured as a top emission struction, and a second organic LED element is on a second portion of the anode and configured as a top emission structure. A first cathode extends into the insulating film and electrically connects the first LED element with the first driver TFT. A second cathode extends into the insulating film and electrically connects the second LED element with the second driver TFT.Type: GrantFiled: January 23, 2003Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Takatoshi Tsujimura, Atsushi Tanaka, Kohichi Miwa, Mitsuo Morooka
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Patent number: 6707513Abstract: An active matrix substrate includes a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, which are sequentially deposited on an insulating substrate. A transparent conductive layer is deposited on the source and drain electrodes so that the transparent conductive layer includes a portion deposited to be substantially the same pattern as those of the source and drain electrodes. The transparent conductive layer is connected to either the source electrode or the drain electrode to form a pixel electrode. A gate line is further included on which the gate insulating film is deposited. The gate line is to be connected to the gate electrode.Type: GrantFiled: July 6, 2001Date of Patent: March 16, 2004Assignee: International Business Machines CorporationInventors: Takatoshi Tsujimura, Osamu Tokuhiro, Kohichi Miwa, Mitsuo Morooka
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Publication number: 20040036072Abstract: A thin film transistor is circular when viewed from top. A first source/drain region is disposed at the center, a semiconductor layer surrounds the first source/drain region and overlaps with an external periphery of the first source/drain region, and a second source/drain region surrounds the semiconductor layer and overlaps the external periphery of the semiconductor layer. The potential of the second source/drain region is set higher than the potential of the first source/drain region. The external periphery of the first source/drain region and the internal periphery of the second source/drain region have concentric circular shapes.Type: ApplicationFiled: August 12, 2003Publication date: February 26, 2004Applicant: CHI MEI OPTOELECTRONICS CORP.Inventors: Takatoshi Tsujimura, Mitsuo Morooka
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Publication number: 20040001037Abstract: A technique to reduce the rate of increase in threshold voltage, i.e. degradation, of an amorphous silicon TFT driving an OLED. A first supply voltage is supplied to a drain of the TFT when a first control voltage is applied to a gate of the TFT to activate the TFT and drive the OLED. However, a second, lower supply voltage is supplied to the drain of the TFT when a second control voltage is applied to the gate of the TFT to deactivate the TFT and turn off the OLED, whereby a voltage differential between the drain and the source when the second control voltage is applied to the gate is substantially lower said first supply voltage. This reduces degradation of the TFT. According to one feature of the present invention, when the TFT is turned off by the absence of voltage applied to its gate, the voltage at the drain of the TFT is reduced to approximately zero to minimize the voltage differential between the drain and the source.Type: ApplicationFiled: March 20, 2003Publication date: January 1, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takatoshi Tsujimura, Kohichi Miwa, Mitsuo Morooka
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Patent number: 6653178Abstract: A thin film transistor and method of making the same is disclosed in which a contact hole is formed with a flattened interface between openings in an inorganic material passivation layer and an organic material interlayer insulating film thereabove. The method includes etching an opening in the interlayer insulating film, using that opening as a mask for subsequently etching a self-aligned opening in the passivation layer, and again etching the interlayer insulating film in a develop back process to obtain a contact hole having a flattened inner sidewall.Type: GrantFiled: January 31, 2002Date of Patent: November 25, 2003Assignee: International Business Machines CorporationInventors: Takatoshi Tsujimura, Taroh Hasumi, Osamu Tokuhiro, Mitsuo Morooka
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Publication number: 20030146711Abstract: An organic LED device comprises a substrate, a first driver TFT on the substrate, a second driver TFT on said substrate, and an insulating film on the substrate, the first driver TFT and the second driver TFT. There is a common anode on the insulating film. A first organic LED element is on a first portion of the anode and configured as a top emission struction, and a second organic LED element is on a second portion of the anode and configured as a top emission structure. A first cathode extends into the insulating film and electrically connects the first LED element with the first driver TFT. A second cathode extends into the insulating film and electrically connects the second LED element with the second driver TFT.Type: ApplicationFiled: January 23, 2003Publication date: August 7, 2003Inventors: Takatoshi Tsujimura, Atsushi Tanaka, Kohichi Miwa, Mitsuo Morooka
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Patent number: 6600196Abstract: The present invention relates to minimizing a leakage current in a floating island portion formed in a thin film transistor. More specifically, the present invention is directed to a thin film transistor including: a source electrode 14 and a drain electrode 15 disposed above an insulating substrate 11 at a predetermined interval; an s-Si film 16 disposed in relation to the source electrode 14 and drain electrode 15; a gate insulating film 17 overlapping the a-Si film 16; and a gate electrode 18 overlapping the gate insulating film 17, in which the a-Si film 16 is disposed between the source electrode 14 and the drain electrode 15 and has a floating island portion 20 above which or beneath which the gate electrode 18 is not formed, and boron ions are implanted into this portion to form a boron-ion-implanted region 19.Type: GrantFiled: January 16, 2001Date of Patent: July 29, 2003Assignee: International Business Machines CorporationInventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
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Publication number: 20030122126Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.Type: ApplicationFiled: December 30, 2002Publication date: July 3, 2003Applicant: International Business Machines CorporationInventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
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Patent number: 6525341Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.Type: GrantFiled: July 20, 2000Date of Patent: February 25, 2003Assignee: International Business Machines CorporationInventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
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Publication number: 20020106839Abstract: A thin film transistor and method of making the same is disclosed in which a contact hole is formed with a flattened interface between openings in an inorganic material passivation layer and an organic material interlayer insulating film thereabove. The method includes etching an opening in the interlayer insulating film, using that opening as a mask for subsequently etching a self-aligned opening in the passivation layer, and again etching the interlayer insulating film in a develop back process to obtain a contact hole having a flattened inner sidewall.Type: ApplicationFiled: January 31, 2002Publication date: August 8, 2002Applicant: International Business Machines CorporationInventors: Takatoshi Tsujimura, Taroh Hasumi, Osamu Tokuhiro, Mitsuo Morooka
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Publication number: 20020016026Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.Type: ApplicationFiled: May 15, 2001Publication date: February 7, 2002Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
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Publication number: 20020003587Abstract: An active matrix substrate includes a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, which are sequentially deposited on an insulating substrate. A transparent conductive layer is deposited on the source and drain electrodes so that the transparent conductive layer includes a portion deposited to be substantially the same pattern as those of the source and drain electrodes. The transparent conductive layer is connected to either the source electrode or the drain electrode to form a pixel electrode. A gate line is further included on which the gate insulating film is deposited. The gate line is to be connected to the gate electrode.Type: ApplicationFiled: July 6, 2001Publication date: January 10, 2002Applicant: IBMInventors: Takatoshi Tsujimura, Osamu Tokuhiro, Kohichi Miwa, Mitsuo Morooka