Patents by Inventor Mitsuru Goto
Mitsuru Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9881691Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: GrantFiled: June 28, 2016Date of Patent: January 30, 2018Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Patent number: 9793007Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.Type: GrantFiled: April 5, 2016Date of Patent: October 17, 2017Assignee: Japan Display Inc.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroyuki Higashijima, Yoshihiro Kotani, Shuuichirou Matsumoto
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Publication number: 20170229080Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first, portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.Type: ApplicationFiled: April 26, 2017Publication date: August 10, 2017Inventors: TAKAYUKI SUZUKI, HIROYUKI ABE, MASAHIRO MAKI, MITSURU GOTO
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Patent number: 9715153Abstract: A display device includes a transparent substrate having a display region with a plurality of scanning signal lines and video signal lines intersecting thereon, a first terminal formed outside the display region connecting to a first terminal wiring and a second terminal wiring connected to a semiconductor chip, and an inverted staggered thin film transistor. The first terminal includes a first portion, a second portion on the first portion, a third portion having an exposed planar terminal plate on the second portion, a plurality of first vias between the first portion and the second portion, and a plurality of second vias between the second portion and the third portion. The first portion is connected to the first and second terminal wirings, and each of the plurality of first vias is not overlapped with each of the plurality of second vias in plan view.Type: GrantFiled: June 8, 2016Date of Patent: July 25, 2017Assignee: Japan Display Inc.Inventors: Takahiro Ochiai, Mitsuru Goto
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Patent number: 9711105Abstract: A gate signal line driving circuit which suppresses noises in a gate signal and a display device which uses the gate signal line driving circuit are provided. A first basic circuit provided to a gate signal line driving circuit includes a HIGH voltage applying switching element which applies a HIGH voltage to gate signal lines in response to a signal HIGH period, and a LOW voltage applying switching circuit which applies a LOW voltage to the gate signal lines in response to a signal LOW period. In response to a signal HIGH period, a switch of the LOW voltage applying switching circuit of the first basic circuit is turned off based on a signal applied to a switch of the HIGH voltage applying switching element of a second basic circuit which assumes a signal HIGH period earlier than the first basic circuit.Type: GrantFiled: September 5, 2014Date of Patent: July 18, 2017Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co. Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Youzou Nakayasu, Yuki Okada, Naoki Takada
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Patent number: 9704447Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.Type: GrantFiled: August 3, 2016Date of Patent: July 11, 2017Assignee: Japan Display Inc.Inventors: Takayuki Suzuki, Hiroyuki Abe, Masahiro Maki, Mitsuru Goto
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Publication number: 20160343327Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.Type: ApplicationFiled: August 3, 2016Publication date: November 24, 2016Inventors: Takayuki SUZUKI, Hiroyuki ABE, Masahiro MAKI, Mitsuru GOTO
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Publication number: 20160307642Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: ApplicationFiled: June 28, 2016Publication date: October 20, 2016Inventors: Takahiro OCHIAI, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Publication number: 20160282660Abstract: A display device includes a transparent substrate having a display region with a plurality of scanning signal lines and video signal lines intersecting thereon, a first terminal formed outside the display region connecting to a first terminal wiring and a second terminal wiring connected to a semiconductor chip, and an inverted staggered thin film transistor. The first terminal includes a first portion, a second portion on the first portion, a third portion having an exposed planar terminal plate on the second portion, a plurality of first vias between the first portion and the second portion, and a plurality of second vias between the second portion and the third portion. The first portion is connected to the first and second terminal wirings, and each of the plurality of first vias is not overlapped with each of the plurality of second vias in plan view.Type: ApplicationFiled: June 8, 2016Publication date: September 29, 2016Inventors: Takahiro Ochiai, Mitsuru Goto
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Patent number: 9437143Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.Type: GrantFiled: November 11, 2015Date of Patent: September 6, 2016Assignee: Japan Display Inc.Inventors: Takayuki Suzuki, Hiroyuki Abe, Masahiro Maki, Mitsuru Goto
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Patent number: 9406399Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: GrantFiled: June 3, 2015Date of Patent: August 2, 2016Assignees: JAPAN DISPLAY INC., PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Publication number: 20160217871Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroyuki HIGASHIJIMA, Yoshihiro KOTANI, Shuuichirou MATSUMOTO
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Patent number: 9389472Abstract: A display device includes a transparent substrate having a display region with a plurality of scanning signal lines and video signal lines intersecting thereon, a first terminal formed outside the display region connecting to a first terminal wiring and a second terminal wiring connected to a semiconductor chip, and an inverted staggered thin film transistor. The first terminal includes a first portion, a second portion on the first portion, a third portion having an exposed planar terminal plate on the second portion, a plurality of first vias between the first portion and the second portion, and a plurality of second vias between the second portion and the third portion. The first portion is connected to the first and second terminal wirings, and each of the plurality of first vias is not overlapped with each of the plurality of second vias in plan view.Type: GrantFiled: September 23, 2014Date of Patent: July 12, 2016Assignee: JAPAN DISPLAY INC.Inventors: Takahiro Ochiai, Mitsuru Goto
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Patent number: 9372375Abstract: A display device includes a TFT substrate with gate signal lines, drain signal lines, thin-film transistors connected thereto, a gate driver connected to the gate signal lines, a drain driver having output terminals connected to drain signal lines, and a film substrate having first wirings. The first wirings are disposed between the drain driver and the film substrate. The drain driver is mounted on the film substrate, and the output terminals are connected to the first wirings between the film substrate and the drain driver. The output terminal includes first group terminals formed in parallel with a longer edge of the drain driver, and second group terminals formed in parallel with the longer edge and disposed between the loner edge and the first group terminals.Type: GrantFiled: October 10, 2013Date of Patent: June 21, 2016Assignees: JAPAN DISPLAY INC., PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.Inventors: Mitsuru Goto, Hiroko Hayata
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Patent number: 9336899Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.Type: GrantFiled: December 22, 2011Date of Patent: May 10, 2016Assignee: Japan Display Inc.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroyuki Higashijima, Yoshihiro Kotani, Shuuichirou Matsumoto
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Patent number: 9214115Abstract: A display device includes a substrate having an image display area, pixel electrodes formed in the image display area of the substrate, a common electrode formed in the image display area of the substrate, inside signal lines formed inside the image display area of the substrate and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area of the substrate and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area of the substrate and electrically connected to the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines include a first portion, and a second portion that is higher in electric resistance than an electric resistance of the first portion, and the second portion has a bend.Type: GrantFiled: October 29, 2014Date of Patent: December 15, 2015Assignee: Japan Display Inc.Inventors: Takayuki Suzuki, Hiroyuki Abe, Masahiro Maki, Mitsuru Goto
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Patent number: 9190006Abstract: A display device includes a plurality of pixel each including a transistor, a pixel electrode connected to the transistor, and a reference electrode disposed so as to be opposite to the pixel electrode. The display device also includes data lines connected to the corresponding pixel circuits, a plurality of gate lines connected to the corresponding pixel circuits, gate circuits each of which sequentially outputs a gate signal, which is in a high voltage level during two or more horizontal periods in a first order or in a second order that is reverse to the first order, and a gate signal control circuit that controls each of the gate circuits and scans the gate lines. The gate signal control circuit controls each of the gate circuits to start to output the gate signals so as not to overlap periods when the gate signals are output to the adjacent gate lines.Type: GrantFiled: March 6, 2012Date of Patent: November 17, 2015Assignee: JAPAN DISPLAY INC.Inventors: Takahiro Ochiai, Mitsuru Goto
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Publication number: 20150270012Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: ApplicationFiled: June 3, 2015Publication date: September 24, 2015Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
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Patent number: 9099053Abstract: A control circuit for a display device includes a shift register circuit which includes at least one transistor and outputs a gate signal in response to at least one voltage signal, a temperature information acquisition unit configured to acquire temperature information at the control circuit for a display device, and a voltage switching unit configured to switch a voltage of the at least one voltage signal based on the acquired temperature information.Type: GrantFiled: February 22, 2011Date of Patent: August 4, 2015Assignees: JAPAN DISPLAY INC., PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.Inventors: Shuuichirou Matsumoto, Mitsuru Goto
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Patent number: 9076403Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: GrantFiled: August 1, 2014Date of Patent: July 7, 2015Assignees: JAPAN DISPLAY INC., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima