Abstract: A liquid crystal display device employing a dot inversion drive method includes a pixel array, a data driver circuit, a short circuit, and a scanning circuit. The short circuit is disposed for respective outputs of the data driver circuit, and includes a switching element for connecting each of the outputs to a precharge voltage different from an output voltage. The short circuit includes the switching element disposed in one of a first switching group and a second switching group; the switching element of one of the first switching group and the second switching group is connected to respective pairs of pixel column units including an odd-numbered pixel column and an even-numbered pixel column which are adjacent to each other; and the pairs of pixel column units which are adjacent to each other are each connected to the switching element disposed in respective switching groups different from each other.

Abstract: A display device includes a TFT substrate with gate signal lines, drain signal lines, thin-film transistors connected thereto, a gate driver connected to the gate signal lines, a drain driver having output terminals connected to drain signal lines, and a film substrate having first wirings. The first wirings are disposed between the drain driver and the film substrate. The drain driver is mounted on the film substrate, and the output terminals are connected to the first wirings between the film substrate and the drain driver. The output terminal includes first group terminals formed in parallel with a longer edge of the drain driver, and second group terminals formed in parallel with the longer edge and disposed between the loner edge and the first group terminals.

Abstract: A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.

Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.

Abstract: To provide a display device including a switching regulator type power generating circuit which realizes an increase in display quality by an output voltage being more stable, and by suppressing a flickering of a screen. A display device includes a switching regulator type direct current power generating circuit, wherein a period for which a switching element is turned on is determined in such a way as to increase or decrease by a given width when a code of an output voltage with respect to a setting voltage is constant, and the period is determined in such a way as to increase or decrease differently from the given width when the code changes.

Abstract: The present invention relates to enhancing low power consumption of a display device having a SRAM. The display device includes a drive circuit receiving video data; video lines connected the drive circuit; and pixels connected to the video signals. The drive circuit includes a memory storing the video data in memory cells. Each memory cell includes a first inverter with input and output terminals connected to first and second nodes, respectively. A second inverter has output and input terminals connected to the first and second nodes, respectively. A First and second transistors between a first data line and the first node each have a control terminal connected to a first word line or a third word line, respectively. Third and fourth transistors between a second data line and the second node each have a control terminal connected to a second word line or a fourth word line, respectively.

Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.

Abstract: A gate signal line driving circuit and a display device includes first and second low voltage application switching elements that supply a low voltage to gate signal lines, a holding capacitor that is connected to a reset target node and supplies an ON signal towards the first and second low voltage application switching elements in a signal low period, first and third control switching elements the one ends of which are connected to the switch input of the first or second low voltage application switching element, and second and fourth control switching elements which each are provided between the switch input of the first or second low voltage application switching element and one end of the holding capacitor. In a startup period, a high voltage is supplied to the holding capacitor through the first to fourth control switching elements.

Abstract: A communication system exchanges electronic mail information. Communication devices are operable to input a telephone number that includes an identification number of a telephone telecommunication services operator and to transmit electronic mail information together with the telephone number. A storage device is operable to store a reference table in which the identification number of a telecommunication services operator is correlated with the domain name of the telecommunication services operator. A communication management device is operable to receive the transmitted electronic mail information and telephone number, to read the domain name of the telecommunication services operator from the reference table using the identification number of the telecommunication services operator, to merge the telephone number with the domain name read from the reference table to form an electronic mail address, and to forward the electronic mail information to the electronic mail address.

Abstract: Each shift register includes a first element controlled by a first potential node to supply a first driving voltage to an output terminal, a second element controlled by a second potential node to supply a second driving voltage lower than the first driving voltage to the output terminal, and a third element for controlling the first potential node and the second potential node so as to have opposite potential levels. Voltages are applied to the third element so that a state of A>B and A>C and a state of A<B and A<C, or a state of A>B and A<C and a state of A<B and A>C, or a state of A<B and A>C and a state of A>B and A<C are switched alternately (A: a gate terminal of the third element, B: a voltage applied to a first terminal thereof, C: a voltage applied to a second terminal thereof).

Abstract: A display device includes a TFT substrate with gate signal lines, drain signal lines, thin-film transistors connected thereto, a gate driver connected to the gate signal lines, a drain driver having output terminals connected to drain signal lines, and a film substrate having first wirings. The first wirings are disposed between the drain driver and the film substrate. The drain driver is mounted on the film substrate, and the output terminals are connected to the first wirings between the film substrate and the drain driver. The output terminal includes first group terminals formed in parallel with a longer edge of the drain driver, and second group terminals formed in parallel with the longer edge and disposed between the loner edge and the first group terminals.

Abstract: Provided are a power supply circuit and a display device which are capable of enhancing power efficiency even when applied to a display panel whose current consumption varies. The power supply circuit boosts and outputs an input voltage using a booster chopper circuit. A frequency control circuit changes a frequency of a clock signal, which controls a switch of the chopper circuit, in accordance with a load of the power supply circuit. The frequency control circuit divides an operation of the display device into a display effective period at a high load and a vertical retrace period at a low load, based on a vertical synchronizing signal and a horizontal synchronizing signal. The frequency control circuit sets the frequency of the clock signal in a high-load period to be higher than that in a low-load period.

Abstract: A display device includes a TFT substrate with gate signal lines, drain signal lines, thin-film transistors connected thereto, a gate driver connected to the gate signal lines, a drain driver having output terminals connected to drain signal lines, and a film substrate having first wirings. The first wirings are disposed between the drain driver and the film substrate. The drain driver is mounted on the film substrate, and the output terminals are connected to the first wirings between the film substrate and the drain driver. The output terminal includes first group terminals formed in parallel with a longer edge of the drain driver, and second group terminals formed in parallel with the longer edge and disposed between the loner edge and the first group terminals.

Abstract: A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.

Abstract: A display device includes a plurality of pixel each including a transistor, a pixel electrode connected to the transistor, and a reference electrode disposed so as to be opposite to the pixel electrode. The display device also includes data lines connected to the corresponding pixel circuits, a plurality of gate lines connected to the corresponding pixel circuits, gate circuits each of which sequentially outputs a gate signal, which is in a high voltage level during two or more horizontal periods in a first order or in a second order that is reverse to the first order, and a gate signal control circuit that controls each of the gate circuits and scans the gate lines. The gate signal control circuit controls each of the gate circuits to start to output the gate signals so as not to overlap periods when the gate signals are output to the adjacent gate lines.

Abstract: A display device includes a terminal group including terminals for supplying a signal to scanning signal lines or the video signal lines via first terminal wiring. Each of the terminals includes: a first portion, which is formed at an end portion of the first terminal wiring, the first portion having an exposed planar terminal surface; and a second portion, which is provided adjacent to the first portion and is formed around the first portion. The second portion is formed of a conductive thin film covered with an insulating film and formed in the same layer as the first terminal wiring or formed in a different layer from the first terminal wiring, and the second portion is electrically connected to the first terminal wiring at a position spaced apart from a connection portion of the first terminal wiring and the first portion.

Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.

Abstract: A display device includes: plural pixel groups each including pixel circuits; plural scanning lines that are each connected to the pixel circuits included in any one of the pixel groups; a clock signal supply circuit that supplies a clock signal including a pulse signal; a shift register circuit that selectively transmits the pulse signal to the scanning lines in a predetermined order; and data signal lines that are connected to the pixel circuits and that supply a data signal to the pixel circuits included in the pixel group to be scanned. The period of the pulse signal supplied to some of the scanning lines is longer than the period of the pulse signal supplied to the other scanning lines, or the data signal is transmitted by the transistors included in the pixel circuits.

Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.

Abstract: A semiconductor integrated circuit includes a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor, and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two frame periods.