Abstract: In a unit drive circuit in each stage in a shift register, a transistor which is maintained in ON state during a period where the unit drive circuit in the stage does not perform an outputting operation is configured not to generate Vth shift. As switches, transistors T6A, T6B are connected between the output terminal OUT and AC power sources VA, VB. At least one of T6A, T6B is brought into ON state and T6A, T6B are alternately brought into OFF state during the period other than the outputting operation period. VA, VB supply L level during a period where T6A, T6B are in ON state, while VA, VB supply a ground potential GND which is an intermediate potential between an H level and an L level during a period where T6A, T6B are in OFF state.

Abstract: A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse Pk in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which Pk?1 and Pk+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which Pk?2 and Pk+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.

Abstract: A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A ?th stage of unit register circuit (38) has two set terminals connected to respective outputs of (??1)th and (?+1)th stages and two reset terminals connected to respective outputs of (?+2)th and (??2)th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.

Abstract: The present invention relates to enhancing low power consumption of a display device having a SRAM. The display device includes a drive circuit receiving video data; video lines connected the drive circuit; and pixels connected to the video signals. The drive circuit includes a memory storing the video data in memory cells. Each memory cell includes a first inverter with input and output terminals connected to first and second nodes, respectively. A second inverter has output and input terminals connected to the first and second nodes, respectively. A First and second transistors between a first data line and the first node each have a control terminal connected to a first word line or a third word line, respectively. Third and fourth transistors between a second data line and the second node each have a control terminal connected to a second word line or a fourth word line, respectively.

Abstract: A semiconductor integrated circuit includes a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor, and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two frame periods.

Abstract: Provided are a display device and a method of driving the same, improving display quality by suppressing abnormal changes resulting from parasitic capacitance. The display device includes first and second pixel circuits having first and second switching elements and first and second display electrodes; and a display control voltage supply unit supplying a display control voltage to the first and second display electrodes. In a first write period, the display control voltage supply unit turns ON the first and second switching elements and supplies a display control voltage corresponding to display data of the first pixel circuit to the first and second display electrodes. In a second write period, the display control voltage supply unit maintains the switch of the second switching element to be in the ON state and supplies a display control voltage corresponding to display data of the second pixel circuit to the second display electrode.

Abstract: A control circuit for a display device includes a shift register circuit which includes at least one transistor and outputs a gate signal in response to at least one voltage signal, a temperature information acquisition unit configured to acquire temperature information at the control circuit for a display device, and a voltage switching unit configured to switch a voltage of the at least one voltage signal based on the acquired temperature information.

Abstract: The present invention provides a liquid crystal display device which can be used in a miniaturized portable equipment, wherein the liquid crystal display device integrally incorporates a drive circuit therein so that a circuit scale can be miniaturized. A liquid crystal drive circuit includes a first drive circuit and a second drive circuit which is mounted on one side of the liquid crystal display panel. One output of the first drive circuit is connected to a plurality of signal lines and the second drive circuit supplies signals to the first drive circuit. The liquid crystal display panel includes holding capacitive elements and signals are supplied to the holding capacitive elements from the second drive circuit. The second drive circuit includes a booster circuit for supplying signals to the first drive circuit and the holding capacitive elements.

Abstract: A semiconductor integrated circuit includes a first register, a second register, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage, and an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor.

Abstract: A gate signal line driving circuit and a display device includes first and second low voltage application switching elements that supply a low voltage to gate signal lines, a holding capacitor that is connected to a reset target node and supplies an ON signal towards the first and second low voltage application switching elements in a signal low period, first and third control switching elements the one ends of which are connected to the switch input of the first or second low voltage application switching element, and second and fourth control switching elements which each are provided between the switch input of the first or second low voltage application switching element and one end of the holding capacitor. In a startup period, a high voltage is supplied to the holding capacitor through the first to fourth control switching elements.

Abstract: A display device includes a drive circuit to which video data is supplied from the outside; video lines to which video signals outputted from the drive circuit are supplied; and pixels to which the video signals are supplied through the video lines. The drive circuit includes a static random access memory which stores the video data in memory cells. The drive circuit is configured to perform writing only on selected memory cells that are connected to shared writing and reading word lines, to drive other memory cells connected to the shared writing and reading word lines and not selected to perform writing to output video data respectively stored therein to a reading data line, and then to rewrite the video data back to the non-selected memory cells, without precharging the memory cells that are connected to shared writing and reading word lines.

Abstract: A display device includes a drive circuit chip, and a substrate on which the drive circuit chip is mounted. The drive circuit chip includes a semiconductor substrate, an insulation layer, a first conductive layer and a second conductive layer formed of metal between the semiconductor substrate and the insulation layer, and a first bump and a second bump formed over the insulation layer. The first bump is superposed with the first conductive layer, and a profile of the first bump in plan view is within a profile of the first conductive layer in plan view. The second bump is superposed with the second conductive layer, and a profile of the second pump in plan view is beyond a profile of the second conductive layer in plan view.

Abstract: A liquid crystal display device employing a dot inversion drive method includes a pixel array, a data driver circuit, a short circuit, and a scanning circuit. The short circuit is disposed for respective outputs of the data driver circuit, and includes a switching element for connecting each of the outputs to a precharge voltage different from an output voltage. The short circuit includes the switching element disposed in one of a first switching group and a second switching group; the switching element of one of the first switching group and the second switching group is connected to respective pairs of pixel column units including an odd-numbered pixel column and an even-numbered pixel column which are adjacent to each other; and the pairs of pixel column units which are adjacent to each other are each connected to the switching element disposed in respective switching groups different from each other.

Abstract: A gate signal line drive circuit and a display device which realize the suppression of a threshold voltage of an element which is used for a long time are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected parallel to each other and are controlled such that at least any one of the plurality of elements is driven by a switching element, and a period during which the element is not driven is set longer than a frame display period.

Abstract: Each shift register includes a first element controlled by a first potential node to supply a first driving voltage to an output terminal, a second element controlled by a second potential node to supply a second driving voltage lower than the first driving voltage to the output terminal, and a third element for controlling the first potential node and the second potential node so as to have opposite potential levels. Voltages are applied to the third element so that a state of A>B and A>C and a state of A<B and A<C, or a state of A>B and A<C and a state of A<B and A>C, or a state of A<B and A>C and a state of A>B and A<C are switched alternately (A: a gate terminal of the third element, B: a voltage applied to a first terminal thereof, C: a voltage applied to a second terminal thereof).

Abstract: A gate signal line driving circuit which suppresses noises in a gate signal and a display device which uses the gate signal line driving circuit are provided. A first basic circuit provided to a gate signal line driving circuit includes a HIGH voltage applying switching element which applies a HIGH voltage to gate signal lines in response to a signal HIGH period, and a LOW voltage applying switching circuit which applies a LOW voltage to the gate signal lines in response to a signal LOW period. In response to a signal HIGH period, a switch of the LOW voltage applying switching circuit of the first basic circuit is turned off based on a signal applied to a switch of the HIGH voltage applying switching element of a second basic circuit which assumes a signal HIGH period earlier than the first basic circuit.

Abstract: A liquid crystal display device includes drain signal lines, gate signal lines, thin film transistors, and a drain driver. The drain driver includes an amplifier circuit having a switching circuit which switches between a first state and a second state, the first state being a state where a first input terminal of the amplifier circuit is coupled to an inverting input terminal and a second input terminal is coupled to a noninverting input terminal, and the second state being a state where the first input terminal is coupled to the noninverting input terminal and the second input terminal is coupled to the inverting input terminal. The amplifier circuit supplies signal voltages to the thin film transistors via the drain signal lines which are gray scale voltages one of plus and minus offset voltages in a first frame and in a second frame.

Abstract: A power circuit includes a coil that charges an electric charge of an input voltage, a switch device that controls charging and discharging of the coil, a diode that rectifies the flow of the electric charge from the coil, a capacitor that stabilizes an output voltage when the switch device is turned on, and a driving circuit that controls ON and OFF states of the switch device. The power circuit alternately switches the ON and OFF states of the switch device to control charging and discharging of the coil and the capacitor, and generates and supplies an output voltage higher than the input voltage, and the driving circuit controls the off-period of the switch device according to the on-period of the switch device and the voltage ratio of the output voltage and the input voltage while changing the repetition period of the ON and OFF states of the switch device.

Abstract: A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.

Abstract: To provide a display device including a switching regulator type power generating circuit which realizes an increase in display quality by an output voltage being more stable, and by suppressing a flickering of a screen. A display device includes a switching regulator type direct current power generating circuit, wherein a period for which a switching element is turned on is determined in such a way as to increase or decrease by a given width when a code of an output voltage with respect to a setting voltage is constant, and the period is determined in such a way as to increase or decrease differently from the given width when the code changes.