Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.

Abstract: In a general aspect, a field-effect transistor (FET) can include a semiconductor region, and a trench disposed in the semiconductor region. The FET can also include a trench gate disposed in an upper portion of the trench in an active region of the FET. The FET can further include a conductive runner disposed in a bottom portion of the trench. The conductive runner can be electrically coupled with a drain terminal of the FET. A portion of the conductive runner can be disposed in the active region below the trench gate.

Abstract: A semiconductor device includes a region of semiconductor material and a trench gate structure. The trench gate structure includes an active trench, a shield dielectric layer in a lower portion of the active trench, and a shield electrode of a first polycrystalline semiconductor material adjacent to the shield dielectric layer. A gate dielectric layer is adjacent to an upper portion of the active trench and a gate electrode of a second polycrystalline semiconductor material is adjacent to the gate dielectric layer. A shield conductive layer of a first conductive material is adjacent to the shield electrode and a gate conductive layer of the first conductive material is adjacent to the gate electrode. A dielectric fill structure is in the active trench electrically isolating the gate electrode and the gate conductive layer from the shield electrode and the shield conductive layer. In some examples, the semiconductor device includes a trench shield contact structure that includes the shield conductive layer.

Abstract: In a general aspect, a field-effect transistor (FET) can include a semiconductor region, and a trench disposed in the semiconductor region. The FET can also include a trench gate disposed in an upper portion of the trench in an active region of the FET. The FET can further include a conductive runner disposed in a bottom portion of the trench. The conductive runner can be electrically coupled with a drain terminal of the FET. A portion of the conductive runner can be disposed in the active region below the trench gate.

Abstract: A semiconductor device includes a region of semiconductor material and a trench gate structure. The trench gate structure includes an active trench, a shield dielectric layer in a lower portion of the active trench, and a shield electrode of a first polycrystalline semiconductor material adjacent to the shield dielectric layer. A gate dielectric layer is adjacent to an upper portion of the active trench and a gate electrode of a second polycrystalline semiconductor material is adjacent to the gate dielectric layer. A shield conductive layer of a first conductive material is adjacent to the shield electrode and a gate conductive layer of the first conductive material is adjacent to the gate electrode. A dielectric fill structure is in the active trench electrically isolating the gate electrode and the gate conductive layer from the shield electrode and the shield conductive layer. In some examples, the semiconductor device includes a trench shield contact structure that includes the shield conductive layer.

Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.

Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.

Abstract: Systems and methods include semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.

Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.

Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.

Abstract: In a semiconductor device in which an IGBT, a control circuit for the IGBT and so on are formed on an SOI substrate divided by trenches, the invention is directed to providing the IGBT with a higher breakdown voltage, an enhanced turn-off characteristic and so on. An N type epitaxial layer is formed on a dummy semiconductor substrate, a trench is formed in the N type epitaxial layer, an N type buffer layer and then a P type embedded collector layer are formed on the sidewall of the trench and the front surface of the N type epitaxial layer, and the bottom of the trench and the P+ type embedded collector layer are covered by an embedded insulation film. The embedded insulation film is covered by a polysilicon film, and a P type semiconductor substrate is attached to the polysilicon film with an insulation film being interposed therebetween.

Abstract: In a conventional semiconductor device, part of a dielectric film of a capacitive element is removed when photoresist is peeled off, and this causes problems of variation in capacitance value of the capacitive element and deterioration of breakdown voltage characteristics. In a semiconductor device according to the present invention, a silicon nitride film serving as a dielectric film is formed on the top face of a lower electrode of a capacitive element, and an upper electrode is formed on the top face of the silicon nitride film. The upper electrode is formed of a laminated structure having a silicon film and a polysilicon film protecting the silicon nitride film. This structure prevents part of the silicon nitride film from being removed when, for example, photoresist is peeled off, thereby preventing variation in capacitance value of the capacitive element and deterioration of the breakdown voltage characteristics.

Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: In a semiconductor device in which an IGBT, a control circuit for the IGBT and so on are formed on an SOI substrate divided by trenches, the invention is directed to providing the IGBT with a higher breakdown voltage, an enhanced turn-off characteristic and so on. An N type epitaxial layer is formed on a dummy semiconductor substrate, a trench is formed in the N type epitaxial layer, an N type buffer layer and then a P type embedded collector layer are formed on the sidewall of the trench and the front surface of the N type epitaxial layer, and the bottom of the trench and the P+ type embedded collector layer are covered by an embedded insulation film. The embedded insulation film is covered by a polysilicon film, and a P type semiconductor substrate is attached to the polysilicon film with an insulation film being interposed therebetween.

Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

Abstract: In a conventional semiconductor device, part of a dielectric film of a capacitive element is removed when photoresist is peeled off, and this causes problems of variation in capacitance value of the capacitive element and deterioration of breakdown voltage characteristics. In a semiconductor device according to the present invention, a silicon nitride film serving as a dielectric film is formed on the top face of a lower electrode of a capacitive element, and an upper electrode is formed on the top face of the silicon nitride film. The upper electrode is formed of a laminated structure having a silicon film and a polysilicon film protecting the silicon nitride film. This structure prevents part of the silicon nitride film from being removed when, for example, photoresist is peeled off, thereby preventing variation in capacitance value of the capacitive element and deterioration of the breakdown voltage characteristics.

Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.