Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A serial communication interface (SCI) cable 4 is provided between the slave processor 2 and the master processor 3. Both processors are connected with a communication interface for peripheral units (SPI: Serial Peripheral Interface) which enables fast transmission. The slave processor 2 transmits a transmission request command which requests at least one of data transmission and reception from the command communication section 220 to the master processor 3 through the SCI cable 4. The master processor 3 transfers data to and from the slave processor 2 in communication with the slave processor 2 by means of the data communication section 310 through the fast SPI cable 5 in response to a transmission request command sent from the slave processor 2 With this, the processing ability of a multi-processor system can be increased.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: An electrical control unit for an automobile of which standby current is smaller. In an electrical control unit for an automobile having a microcomputer, an input circuit, a driver circuit, and a power supply circuit, which is started by a wake-up signal from the circuit other than the ignition switch even when the ignition switch of the automobile is cut off, the microcomputer is started by shifting the power supply circuit from an inert state to an active state to generate the voltage for operating the microcomputer, and the predetermined processing is executed.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: An electrical control unit for an automobile of which standby current is smaller. In an electrical control unit for an automobile having a microcomputer, an input circuit, a driver circuit, and a power supply circuit, which is started by a wake-up signal from the circuit other than the ignition switch even when the ignition switch of the automobile is cut off, the microcomputer is started by shifting the power supply circuit from an inert state to an active state to generate the voltage for operating the microcomputer, and the predetermined processing is executed.

Abstract: An electrical control unit for an automobile of which standby current is smaller. In an electrical control unit for an automobile having a microcomputer, an input circuit, a driver circuit, and a power supply circuit, which is started by a wake-up signal from the circuit other than the ignition switch even when the ignition switch of the automobile is cut off, the microcomputer is started by shifting the power supply circuit from an inert state to an active state to generate the voltage for operating the microcomputer, and the predetermined processing is executed.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: An engine electronic control unit is inserted through a through hole provided in an intake pipe and mounted in an intake air passage in a direction substantially perpendicularly with respect to a plane of the intake pipe forming the intake air passage. This unit is then secured to the intake pipe using a fixing flange provided at a connector portion. A fixing rail is protruded inside the intake pipe and leading edges of a metal base and a metal cover of the unit are inserted into this rail, thereby securing in position an end opposite to a side of the connector portion of the unit. This realizes an engine electronic control unit offering an outstanding heat radiation performance and vibration resistance, without having to provide special heat radiating parts or without involving an increase in an intake air resistance within the intake air passage. By using such an engine electronic control unit, it is possible to provide a low-cost, compact engine air intake system.

Abstract: A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have an independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.

Abstract: An engine electronic control unit is inserted through a through hole provided in an intake pipe and mounted in an intake air passage in a direction substantially perpendicularly with respect to a plane of the intake pipe forming the intake air passage. This unit is then secured to the intake pipe using a fixing flange provided at a connector portion. A fixing rail is protruded inside the intake pipe and leading edges of a metal base and a metal cover of the unit are inserted into this rail, thereby securing in position an end opposite to a side of the connector portion of the unit.

Abstract: A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have a independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have an independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.

Abstract: An engine electronic control unit is inserted through a through hole provided in an intake pipe and mounted in an intake air passage in a direction substantially perpendicularly with respect to a plane of the intake pipe forming the intake air passage. This unit is then secured to the intake pipe using a fixing flange provided at a connector portion. A fixing rail is protruded inside the intake pipe and leading edges of a metal base and a metal cover of the unit are inserted into this rail, thereby securing in position an end opposite to a side of the connector portion of the unit. This realizes an engine electronic control unit offering an outstanding heat radiation performance and vibration resistance, without having to provide special heat radiating parts or without involving an increase in an intake air resistance within the intake air passage. By using such an engine electronic control unit, it is possible to provide a low-cost, compact engine air intake system.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.