Patents by Inventor Mitsuru Watabe

Mitsuru Watabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020092508
    Abstract: A heating device is capable of efficiently heat a heated body as heating object. The heating device includes a heating body, a power source for supplying a current to the heating body, a current control element controlling current flowing through the heating body, and a heat conductive body to be thermally coupled with the heating body and the current control element for transmitting heat generated by the heating body and heat generated by the current control element to a heating object.
    Type: Application
    Filed: August 10, 2001
    Publication date: July 18, 2002
    Applicant: Hitachi Ltd.
    Inventors: Nobuyasu Kanekawa, Kohei Sakurai, Mitsuru Watabe, Shoji Sasaki, Kenji Tabuchi, Toshio Hayashibara
  • Publication number: 20020073962
    Abstract: Even in such an arrangement in which the throttle valve is operated independently of the engine control system, abnormal engine behavior is ensured to be detected such that a necessary fail-safe operation should be taken. The arrangement of the invention is comprised of the electronically controlled throttle system, engine control system and engine speed monitoring unit, wherein the electronically controlled throttle system is allowed to monitor engine behaviors. Thereby, in the case when the throttle valve is operated independently of the engine control system, if its engine behavior becomes abnormal relative to its drive contents, the engine system senses the abnormality, and takes a fail-safe operation such as to stop operation of the throttle valve and the like.
    Type: Application
    Filed: February 21, 2002
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Tsugio Tomita, Syuuichi Nakano, Koichi Ono, Mitsuru Watabe
  • Publication number: 20020078325
    Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
    Type: Application
    Filed: December 11, 2001
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6390064
    Abstract: An apparatus of controlling an electronically controllable throttle valve for car has a sensor for detecting the opening of the throttle valve and a microcomputer. A throttle valve opening command value is delivered in the form of a digital signal under the control of the microcomputer. The digital command value signal is converted into an analog signal and on the basis of the analog signal and a detected throttle opening, a motor connected to the throttle valve is driven to control the opening thereof.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: May 21, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Katsuji Marumoto, Masatoshi Hoshino, Ryozo Masaki, Minoru Ohsuga, Mitsuru Watabe
  • Publication number: 20020029098
    Abstract: To provide a low-cost vehicle control system and a car using the system by making radiation of an actuator driver easy and thereby reducing the radiation component cost and moreover, downsizing an electronic control unit and improving the versatility.
    Type: Application
    Filed: March 9, 2001
    Publication date: March 7, 2002
    Applicant: Hitachi Ltd.
    Inventors: Kohei Sakurai, Nobuyasu Kanekawa, Fumio Murabayashi, Mitsuru Watabe, Toshio Hayashibara
  • Patent number: 6352064
    Abstract: Even in such an arrangement in which the throttle valve is operated independently of the engine control system, abnormal engine behavior is ensured to be detected such that a necessary fail-safe operation should be taken. The arrangement of the invention is comprised of the electronically controlled throttle system, engine control system and engine speed monitoring unit, wherein the electronically controlled throttle system is allowed to monitor engine behaviors. Thereby, in the case when the throttle valve is operated independently of the engine control system, if its engine behavior becomes abnormal relative to its drive contents, the engine system senses the abnormality, and takes a fail-safe operation such as to stop operation of the throttle valve and the like.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: March 5, 2002
    Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.
    Inventors: Tsugio Tomita, Syuuichi Nakano, Koichi Ono, Mitsuru Watabe
  • Patent number: 6343357
    Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: January 29, 2002
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6288728
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: September 11, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Publication number: 20010015196
    Abstract: An apparatus of controlling an electronically controllable throttle valve for car has a sensor for detecting the opening of the throttle valve and a microcomputer. A throttle valve opening command value is delivered in the form of a digital signal under the control of the microcomputer. The digital command value signal is converted into an analog signal and on the basis of the analog signal and a detected throttle opening, a motor connected to the throttle valve is driven to control the opening thereof.
    Type: Application
    Filed: April 24, 2001
    Publication date: August 23, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Katsuji Marumoto, Masatoshi Hoshino, Ryozo Masaki, Minoru Ohsuga, Mitsuru Watabe
  • Patent number: 6272620
    Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: August 7, 2001
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6253733
    Abstract: An apparatus of controlling an electronically controllable throttle valve for car has a sensor for detecting the opening of the throttle valve and a microcomputer. A throttle valve opening command value is delivered in the form of a digital signal under the control of the microcomputer. The digital command value signal is converted into an analog signal and on the basis of the analog signal and a detected throttle opening, a motor connected to the throttle valve is driven to control the opening thereof.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: July 3, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Katsuji Marumoto, Masatoshi Hoshino, Ryozo Masaki, Minoru Ohsuga, Mitsuru Watabe
  • Patent number: 6253308
    Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: June 26, 2001
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6205535
    Abstract: A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6131154
    Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: October 10, 2000
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6122724
    Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: September 19, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6097404
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: August 1, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 6091863
    Abstract: An image processor which is connected to a system bus that connects a processor for forming graphic command related to image processing to a main memory that holds command and original image data, and draws image on the frame buffer based upon said graphic command from said processor, wherein said graphic processor has a data bus change-over unit which connects said system bus to a first data bus that is connected to a graphic data memory holding said graphic command and said original image data, or connects said first data bus to a frame buffer which holds the data to be displayed. The image processor realizes a high-speed processing at a reduced cost by using a graphic memory bus coupled to a graphic processor.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: July 18, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Keisuke Nakashima, Jun Satoh, Kazushige Yamagishi, Takashi Miyamoto, Kenichiro Omura, Koyo Katsura, Mitsuru Watabe
  • Patent number: 6055960
    Abstract: An apparatus of controlling an electronically controllable throttle valve for car has a sensor for detecting the opening of the throttle valve and a microcomputer. A throttle valve opening command value is delivered in the form of a digital signal under the control of the microcomputer. The digital command value signal is converted into an analog signal and on the basis of the analog signal and a detected throttle opening, a motor connected to the throttle valve is driven to control the opening thereof.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: May 2, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Katsuji Marumoto, Masatoshi Hoshino, Ryozo Masaki, Minoru Ohsuga, Mitsuru Watabe
  • Patent number: 5999197
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: December 7, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 5991545
    Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 23, 1999
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe