Patents by Inventor Mitsuya Sato

Mitsuya Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4677474
    Abstract: A probing apparatus for use in examination of a chip formed on a wafer, in co-operation with a sheet-like member having probe needles to be contacted to the chip on the wafer, the probing apparatus being arranged so that the positions of the probe needles of the sheet-like member, when it is held by a holder of the probing apparatus, are detected automatically and, in accordance with the detected positions, the sheet-like member is displaced automatically so as to be aligned with the probing apparatus. According to another aspect of the invention, the position of the wafer when it is at a location under the probe needles is detected automatically and, in accordance with the detected position, the wafer is displaced so as to be aligned with the sheet-like member which has been aligned automatically with the probing apparatus.
    Type: Grant
    Filed: June 27, 1985
    Date of Patent: June 30, 1987
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mitsuya Sato, Bunei Hamasaki
  • Patent number: 4659227
    Abstract: An apparatus for aligning objects on the basis of a signal obtained by scanning marks formed on the objects. A position datum representing the relative position between the objects is extracted on the basis of an extraction level. The marks are scanned a plurality of times and an average is obtained by the plural data provided on the basis of the extraction datum. Those operations are repeated with one or more different extraction levels. In each of the data group corresponding to one of the extraction data, a peculiar or exceptional datum is determined. Among the peculiar data obtained for individual sets of data, a minimum is selected. Thus, an extraction datum which results in the minimum peculiar datum is determined. The average of the position data obtained with this extraction datum is used for bringing the objects into alignment with each other.
    Type: Grant
    Filed: February 8, 1985
    Date of Patent: April 21, 1987
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mitsuya Sato, Minoru Yomoda
  • Patent number: 4569562
    Abstract: In a method of and an apparatus for controlling a fluid bearing, a state in which the power source of a control system is switched off (an open state) or a state in which a predetermined pressure different from the OFF condition is provided (a stopped state) is established when an abnormal condition in which the pressure reaches a predetermined value exceeding a servo-controlled upper or lower limit occurs, whereby the pressure of the fluid bearing is held within a safe pressure range.
    Type: Grant
    Filed: October 19, 1983
    Date of Patent: February 11, 1986
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mitsuya Sato, Isamu Shimoda
  • Patent number: 4543499
    Abstract: A semiconductor integrated circuit includes low voltage operation circuitries such as I.sup.2 L and high voltage operation circuitries operating at a higher voltage than the low voltage operation circuitries. Both of the low and high voltage operation circuitries are implemented in a single semiconductor chip in coexistence with each other. The low voltage operation circuitries are disposed in constant current paths in the high voltage operation circuitries so that the currents once used by the high voltage operation circuits are utilized again by the low voltage operation circuitries. Power dissipation of the whole integrated circuit is thus reduced significantly.
    Type: Grant
    Filed: April 8, 1982
    Date of Patent: September 24, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Kaneko, Minoru Nagata, Makoto Furihata, Setsuo Ogura, Takahiro Okabe, Mitsuya Sato
  • Patent number: 4496239
    Abstract: Disclosed is an apparatus for exposing a wafer to a projected image of a mask, and including a mask holder for holding the mask, a wafer holder for holding the wafer, a projection optical system for projecting the image of the mask upon the wafer, a guide path extending along a scanning direction, a plurality of sliders sliding on the guide path, a movable member coupling the mask holder and the wafer holder and placed on the sliders, a heater for compensating for the magnification error of the image in a direction orthogonal to the scanning direction attributable to the projection optical system and for producing a temperature distribution in one of the mask and the wafer, and a controller for compensating for the magnification error of the image in the scanning direction and the error of right angle attributable to the guide path and for controlling the posture of the movable member during the movement thereof.
    Type: Grant
    Filed: November 9, 1982
    Date of Patent: January 29, 1985
    Assignee: Canon Kabushiki Kaisha
    Inventors: Junji Isohata, Mitsuya Sato
  • Patent number: 4276560
    Abstract: In a color signal reproducing circuit, a red color difference signal from a color demodulator circuit is corrected by a blue color difference signal, and the blue color difference signal is corrected by a luminance signal. The phase of a color subcarrier signal to be supplied to the color demodulator circuit is controlled by the corrected red color difference signal during reception of a VIR signal, and the level of a color signal to be supplied to the color demodulator circuit is controlled by the corrected blue color difference signal. The controls of hue and color saturation are facilitated by the use of the corrected color difference signals. It is also made possible to deliver from the color demodulator circuit, color difference signals which match the fluorescence characteristics of a color picture tube.
    Type: Grant
    Filed: November 28, 1978
    Date of Patent: June 30, 1981
    Assignees: Hitachi, Ltd., Victor Company of Japan, Limited
    Inventors: Yasuaki Watanabe, Yukio Okabe, Shinichi Kojima, Mitsuya Sato
  • Patent number: 3969637
    Abstract: A transistor circuit comprises a cancellation circuit which receives, as an input signal, an output signal of a signal circuit having at least a connection wiring and which supplies to the connection wiring a cancellation current opposite in phase and substantially equal in magnitude to a signal current supplied to the connection wiring by the signal circuit, whereby a signal voltage due to the signal current and the distributed resistance of the connection wiring is prevented from being produced.
    Type: Grant
    Filed: June 25, 1975
    Date of Patent: July 13, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Norio Minami, Mitsuya Sato
  • Patent number: 3961360
    Abstract: In a synchronizing detector circuit which has at least two differential transistors, a pair of constant current transistors are connected to the differential transistors, and an output transistor is connected to the junctures between the differential and constant current transistors and to a filter circuit for detection. A synchronizing detector circuit comprises a compensating circuit incorporated between the junctures and the filter circuit and includes a constant current absorbing circuit, so as to prevent an offset output voltage of the filter circuit due to noise.
    Type: Grant
    Filed: September 9, 1974
    Date of Patent: June 1, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuya Sato, Yozo Tanihara, Makoto Furihata