Patents by Inventor Mitsuyoshi Endo
Mitsuyoshi Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190080953Abstract: A manufacturing apparatus includes a first supporting section to support a first tape section. The first tape section has a first surface facing away from the first supporting section. For example, a semiconductor chip can be disposed on the first surface. A second supporting section of the apparatus supports a second tape section in a facing arrangement with the first tape section. The second tape section has a second surface facing away from the second supporting section. For example, a semiconductor chip can be transferred from the first surface to the second surface in a manufacturing process. A ring element is between the first and second tape sections and surrounds a space between the first and second tape sections. The ring element has a port allowing fluid communication between the space and an outlet port.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Inventors: Shuji Itonaga, Hideto Furuyama, Mitsuyoshi Endo
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Patent number: 10170352Abstract: A manufacturing apparatus includes a first supporting section to support a first tape section. The first tape section has a first surface facing away from the first supporting section. For example, a semiconductor chip can be disposed on the first surface. A second supporting section of the apparatus supports a second tape section in a facing arrangement with the first tape section. The second tape section has a second surface facing away from the second supporting section. For example, a semiconductor chip can be transferred from the first surface to the second surface in a manufacturing process. A ring element is between the first and second tape sections and surrounds a space between the first and second tape sections. The ring element has a port allowing fluid communication between the space and an outlet port.Type: GrantFiled: March 1, 2015Date of Patent: January 1, 2019Assignee: ALPAD CORPORATIONInventors: Shuji Itonaga, Hideto Furuyama, Mitsuyoshi Endo
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Patent number: 9887328Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a sealing member configured to cover a lower surface of the semiconductor layer and a side surface of the semiconductor layer to protrude to be higher than an upper surface of the semiconductor layer at a side of the semiconductor layer, a fluorescer layer provided above the semiconductor layer and the sealing member, and an insulating film provided between the sealing member and the semiconductor layer and between the sealing member and the fluorescer layer. A corner of a protruding portion of the sealing member is rounded.Type: GrantFiled: July 10, 2014Date of Patent: February 6, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Tomizawa, Akihiro Kojima, Miyoko Shimada, Yosuke Akimoto, Hideko Mukaida, Mitsuyoshi Endo, Hideto Furuyama, Yoshiaki Sugizaki, Kazuo Fujimura, Shinya Ito, Shinji Nunotani
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Patent number: 9755127Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer including a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first surface, and a second surface; a p-side electrode; an n-side electrode; a first p-side pillar; a first n-side pillar; a first insulating layer; a fluorescer layer; a second insulating layer; a p-side interconnect; and an n-side interconnect. The second insulating layer is provided as one body in at least a portion of an outer side of a side surface of the first insulating layer and at least a portion of an outer side of a side surface of the fluorescer layer.Type: GrantFiled: March 10, 2016Date of Patent: September 5, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Miyuki Shimojuku, Hideto Furuyama, Shuji Itonaga, Mitsuyoshi Endo, Yukihiro Nomura, Akihiro Kojima
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Patent number: 9735325Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes the transferring a first group from a first support to a second support; the deforming the second support to convert each pitch of the semiconductor chips in the first group transferred on the second support into a second pitch different from the first pitch; the forming an insulating layer around each of the semiconductor chips, the insulating layer covering each of the semiconductor chips in the first group arranged in the second pitch; and the dicing the insulating layer. The first group is selected from a plurality of semiconductor chips supported by the first support. The plurality of semiconductor chips is arranged in an initial pitch. The first group is arranged in a first pitch being longer than the initial pitch.Type: GrantFiled: March 4, 2015Date of Patent: August 15, 2017Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuyoshi Endo
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Publication number: 20170077367Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer including a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first surface, and a second surface; a p-side electrode; an n-side electrode; a first p-side pillar; a first n-side pillar; a first insulating layer; a fluorescer layer; a second insulating layer; a p-side interconnect; and an n-side interconnect. The second insulating layer is provided as one body in at least a portion of an outer side of a side surface of the first insulating layer and at least a portion of an outer side of a side surface of the fluorescer layer.Type: ApplicationFiled: March 10, 2016Publication date: March 16, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: MIYUKI SHIMOJUKU, HIDETO FURUYAMA, SHUJI ITONAGA, MITSUYOSHI ENDO, YUKIHIRO NOMURA, AKIHIRO KOJIMA
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Patent number: 9595631Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer having a first layer including an n-type semiconductor, a second layer including a p-type semiconductor, a light emitting layer, a first surface, and a second surface opposite to the first surface; an n-side electrode; a p-side electrode; a third layer; an insulating member; an n-side metal portion; and a p-side metal portion. The insulating member has a lower surface. A height of the lower surface is higher than a height of the first surface. The insulating member covers a periphery of the third layer, and has light reflectivity on at least a surface of a part adjacent to a side surface of the third layer.Type: GrantFiled: August 13, 2015Date of Patent: March 14, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuyoshi Endo, Shuji Itonaga, Miyuki Shimojuku, Yukihiro Nomura, Hideto Furuyama
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Patent number: 9543484Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer including a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first surface, and a second surface, the light emitting layer provided between the first semiconductor layer and the second semiconductor layer, the second surface opposing the first surface; a p-side electrode; an n-side electrode; a p-side pillar; an n-side pillar; a first insulating layer; an optical layer; a second insulating layer; a first layer; a p-side interconnect; and an n-side interconnect. The first layer includes a first lower end portion and a second lower end portion.Type: GrantFiled: March 9, 2016Date of Patent: January 10, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuyoshi Endo, Shuji Itonaga, Miyuki Shimojuku, Yukihiro Nomura, Hideto Furuyama
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Publication number: 20160268471Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer having a first layer including an n-type semiconductor, a second layer including a p-type semiconductor, a light emitting layer, a first surface, and a second surface opposite to the first surface; an n-side electrode; a p-side electrode; a third layer; an insulating member; an n-side metal portion; and a p-side metal portion. The insulating member has a lower surface. A height of the lower surface is higher than a height of the first surface. The insulating member covers a periphery of the third layer, and has light reflectivity on at least a surface of a part adjacent to a side surface of the third layer.Type: ApplicationFiled: August 13, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Mitsuyoshi Endo, Shuji Itonaga, Miyuki Shimojuku, Yukihiro Nomura, Hideto Furuyama
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Publication number: 20160233389Abstract: According to one embodiment, a semiconductor light emitting device includes a light emitting element and a phosphor layer provided on the light emitting element. The phosphor layer includes a plurality of phosphor particles and a plurality of inorganic particles having smaller sizes than the phosphor particles. The phosphor particles are bound together with aggregation of the inorganic particles and the phosphor particles.Type: ApplicationFiled: August 26, 2015Publication date: August 11, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hideto FURUYAMA, Mitsuyoshi ENDO, Miyuki SHIMOJUKU, Shuji ITONAGA, Yukihiro NOMURA
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Patent number: 9312207Abstract: A semiconductor device including a semiconductor substrate having a first surface and a second surface, the first surface being configured for formation of a semiconductor element; a through hole extending through the semiconductor substrate; and a through electrode disposed in the through hole. The through electrode includes an insulating film disposed along a sidewall of the through hole, a conductive layer comprising a first material disposed along the insulating film, and an electrode layer comprising a second material filled inside the through hole over the conductive layer. The first material is softer than the second material. The second material has a melting point higher than a melting point of the first material. The electrode layer includes a void portion being closed near the second surface of the semiconductor substrate.Type: GrantFiled: September 12, 2014Date of Patent: April 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Wakatsuki, Atsuko Sakata, Kengo Uchida, Kazuyuki Higashi, Mitsuyoshi Endo
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Publication number: 20160079112Abstract: A manufacturing apparatus includes a first supporting section to support a first tape section. The first tape section has a first surface facing away from the first supporting section. For example, a semiconductor chip can be disposed on the first surface. A second supporting section of the apparatus supports a second tape section in a facing arrangement with the first tape section. The second tape section has a second surface facing away from the second supporting section. For example, a semiconductor chip can be transferred from the first surface to the second surface in a manufacturing process. A ring element is between the first and second tape sections and surrounds a space between the first and second tape sections. The ring element has a port allowing fluid communication between the space and an outlet port.Type: ApplicationFiled: March 1, 2015Publication date: March 17, 2016Inventors: Shuji ITONAGA, Hideto FURUYAMA, Mitsuyoshi ENDO
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Publication number: 20160079491Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes the transferring a first group from a first support to a second support; the deforming the second support to convert each pitch of the semiconductor chips in the first group transferred on the second support into a second pitch different from the first pitch; the forming an insulating layer around each of the semiconductor chips, the insulating layer covering each of the semiconductor chips in the first group arranged in the second pitch; and the dicing the insulating layer. The first group is selected from a plurality of semiconductor chips supported by the first support. The plurality of semiconductor chips is arranged in an initial pitch. The first group is arranged in a first pitch being longer than the initial pitch.Type: ApplicationFiled: March 4, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Mitsuyoshi ENDO
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Patent number: 9229052Abstract: According to one embodiment, a stack includes first and second wiring structures and an inspection circuit. The inspection circuit includes a switching circuit having an input terminal, a drive terminal, and an output terminal electrically connected with a discharge mechanism. The inspection circuit is configured such that, in a state where a first electric connection is made in the first wiring structure and a second electric connection is made in the second wiring structure, at the time of applying charges to first and second electrodes, the charge applied to the second electrode flows to the drive terminal through the second wiring structure to bring the input terminal and the output terminal of the switching circuit into an electrically conducted state, and the charge applied to the first electrode flows to the discharge mechanism through the first wiring structure and the switching circuit.Type: GrantFiled: July 18, 2013Date of Patent: January 5, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuyoshi Endo
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Patent number: 9209097Abstract: According to one embodiment, there is provided a substrate bonding method. The substrate bonding method includes disposing a first substrate and a second substrate to face each other. The substrate bonding method includes controlling the first substrate and the second substrate to have a temperature difference. The substrate bonding method includes, in a state where the first substrate and the second substrate are controlled to have the temperature difference, bonding the first substrate to the second substrate by bringing the first substrate into contact with the second substrate while deforming the first substrate so that a central portion of the first substrate is projected toward the second substrate. The central portion of the first substrate is on an inner side of a peripheral portion of the first substrate.Type: GrantFiled: March 5, 2014Date of Patent: December 8, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuyoshi Endo
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Publication number: 20150262913Abstract: A semiconductor device including a semiconductor substrate having a first surface and a second surface, the first surface being configured for formation of a semiconductor element; a through hole extending through the semiconductor substrate; and a through electrode disposed in the through hole. The through electrode includes an insulating film disposed along a sidewall of the through hole, a conductive layer comprising a first material disposed along the insulating film, and an electrode layer comprising a second material filled inside the through hole over the conductive layer. The first material is softer than the second material. The second material has a melting point higher than a melting point of the first material. The electrode layer includes a void portion being closed near the second surface of the semiconductor substrate.Type: ApplicationFiled: September 12, 2014Publication date: September 17, 2015Inventors: Satoshi WAKATSUKI, Atsuko SAKATA, Kengo UCHIDA, Kazuyuki HIGASHI, Mitsuyoshi ENDO
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Patent number: 9123717Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.Type: GrantFiled: July 30, 2013Date of Patent: September 1, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kenro Nakamura, Mitsuyoshi Endo, Kazuyuki Higashi, Takashi Shirono
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Publication number: 20150140689Abstract: According to one embodiment, there is provided a substrate bonding method. The substrate bonding method includes disposing a first substrate and a second substrate to face each other. The substrate bonding method includes controlling the first substrate and the second substrate to have a temperature difference. The substrate bonding method includes, in a state where the first substrate and the second substrate are controlled to have the temperature difference, bonding the first substrate to the second substrate by bringing the first substrate into contact with the second substrate while deforming the first substrate so that a central portion of the first substrate is projected toward the second substrate. The central portion of the first substrate is on an inner side of a peripheral portion of the first substrate.Type: ApplicationFiled: March 5, 2014Publication date: May 21, 2015Inventor: Mitsuyoshi ENDO
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Publication number: 20150069437Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a sealing member configured to cover a lower surface of the semiconductor layer and a side surface of the semiconductor layer to protrude to be higher than an upper surface of the semiconductor layer at a side of the semiconductor layer, a fluorescer layer provided above the semiconductor layer and the sealing member, and an insulating film provided between the sealing member and the semiconductor layer and between the sealing member and the fluorescer layer. A corner of a protruding portion of the sealing member is rounded.Type: ApplicationFiled: July 10, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hideyuki TOMIZAWA, Akihiro KOJIMA, Miyoko SHIMADA, Yosuke AKIMOTO, Hideko MUKAIDA, Mitsuyoshi ENDO, Hideto FURUYAMA, Yoshiaki SUGIZAKI, Kazuo FUJIMURA, Shinya ITO, Shinji NUNOTANI
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Patent number: 8884396Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.Type: GrantFiled: September 21, 2011Date of Patent: November 11, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuyoshi Endo