Patents by Inventor Mitsuyoshi Endo

Mitsuyoshi Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140285273
    Abstract: According to one embodiment, there is provided a semiconductor device including a first capacitance electrode, a second capacitance electrode, and a depletion layer. The first capacitance electrode is buried in a hole via an insulating film. The hole is formed in a semiconductor substrate. The second capacitance electrode is formed on a front surface side or on a back surface side of the semiconductor substrate so as to be separated from the first capacitance electrode. The depletion layer forming mechanism includes a control electrode, and forms a depletion layer between the first capacitance electrode and the second capacitance electrode.
    Type: Application
    Filed: July 10, 2013
    Publication date: September 25, 2014
    Inventor: Mitsuyoshi ENDO
  • Publication number: 20140242779
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.
    Type: Application
    Filed: July 30, 2013
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenro NAKAMURA, Mitsuyoshi ENDO, Kazuyuki HIGASHI, Takashi SHIRONO
  • Publication number: 20140210497
    Abstract: According to one embodiment, a stack includes first and second wiring structures and an inspection circuit. The inspection circuit includes a switching circuit having an input terminal, a drive terminal, and an output terminal electrically connected with a discharge mechanism. The inspection circuit is configured such that, in a state where a first electric connection is made in the first wiring structure and a second electric connection is made in the second wiring structure, at the time of applying charges to first and second electrodes, the charge applied to the second electrode flows to the drive terminal through the second wiring structure to bring the input terminal and the output terminal of the switching circuit into an electrically conducted state, and the charge applied to the first electrode flows to the discharge mechanism through the first wiring structure and the switching circuit.
    Type: Application
    Filed: July 18, 2013
    Publication date: July 31, 2014
    Inventor: Mitsuyoshi ENDO
  • Patent number: 8766407
    Abstract: According to one embodiment, a semiconductor wafer includes a semiconductor substrate and an interconnect layer formed on the semiconductor substrate. In the semiconductor wafer, the semiconductor substrate includes a first region that is located on the outer periphery side of the semiconductor substrate and that is not covered with the interconnect layer. The interconnect layer includes a second region where the upper surface of the interconnect layer is substantially flat. A first insulating film is formed in the first region. The upper surface of the interconnect layer within the second region and the upper surface of the first insulating film substantially flush with each other.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuyoshi Endo
  • Publication number: 20130168832
    Abstract: According to one embodiment, a semiconductor device is provided such that a penetrating via with a conductive material embedded through a medium of an insulating film is formed in a through hole of a p-type semiconductor substrate. The semiconductor device includes an n-type well on an upper section of the p-type semiconductor substrate in the vicinity of the penetrating via, an electrode connected to the n-type well, and the electrode connected to the p-type semiconductor substrate in the vicinity of the electrode.
    Type: Application
    Filed: September 7, 2012
    Publication date: July 4, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mitsuyoshi ENDO
  • Patent number: 8427808
    Abstract: A variable capacity element has a substrate, a pair of capacitor electrodes, a pair of driver electrodes, and a pair of capacitor wirings why one of the capacitor electrodes is movable by applying a voltage between the driver electrodes. A pair of driver electrodes are connected to the pair of capacitor electrodes, being insulated from the capacitor electrodes. A pair of capacitor wiring extend in parallel each other from connecting portions with the pairs of the capacitor electrodes, being electrically connected with the capacitor electrodes.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuyoshi Endo
  • Publication number: 20130049210
    Abstract: According to one embodiment, a semiconductor wafer includes a semiconductor substrate and an interconnect layer formed on the semiconductor substrate. In the semiconductor wafer, the semiconductor substrate includes a first region that is located on the outer periphery side of the semiconductor substrate and that is not covered with the interconnect layer. The interconnect layer includes a second region where the upper surface of the interconnect layer is substantially flat. A first insulating film is formed in the first region. The upper surface of the interconnect layer within the second region and the upper surface of the first insulating film substantially flush with each other.
    Type: Application
    Filed: February 3, 2012
    Publication date: February 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mitsuyoshi ENDO
  • Patent number: 8324715
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a first insulating layer, an electrode pad, a through hole, a second insulating layer, and a conductive material. A through groove passes through the semiconductor substrate from a surface to an opposite surface. The first insulating layer fills the through groove. The electrode pad is connected with an interconnection layer. The second insulating layer is provided between the electrode pad and the first insulating layer. The through hole communicates with the electrode pad and passes through the first insulating layer and the second insulating layer. The conductive material is provided in the through hole so as to be connected with the electrode pad.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: December 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuyoshi Endo
  • Publication number: 20120248579
    Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: October 4, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mitsuyoshi ENDO
  • Publication number: 20120248624
    Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.
    Type: Application
    Filed: December 1, 2011
    Publication date: October 4, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mitsuyoshi Endo
  • Publication number: 20120038029
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a first insulating layer, an electrode pad, a through hole, a second insulating layer, and a conductive material. A through groove passes through the semiconductor substrate from a surface to an opposite surface. The first insulating layer fills the through groove. The electrode pad is connected with an interconnection layer. The second insulating layer is provided between the electrode pad and the first insulating layer. The through hole communicates with the electrode pad and passes through the first insulating layer and the second insulating layer. The conductive material is provided in the through hole so as to be connected with the electrode pad.
    Type: Application
    Filed: July 11, 2011
    Publication date: February 16, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mitsuyoshi Endo
  • Publication number: 20110007448
    Abstract: A variable capacity element has a substrate, a pair of capacitor electrodes, a pair of driver electrodes, and a pair of capacitor wirings why one of the capacitor electrodes is movable by applying a voltage between the driver electrodes. A pair of driver electrodes are connected to the pair of capacitor electrodes, being insulated from the capacitor electrodes. A pair of capacitor wiring extend in parallel each other from connecting portions with the pairs of the capacitor electrodes, being electrically connected with the capacitor electrodes.
    Type: Application
    Filed: March 1, 2010
    Publication date: January 13, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mitsuyoshi Endo
  • Patent number: 7768456
    Abstract: First and second wires are formed so that the further away from a semiconductor chip, the greater the distance between the first and second wires. This prevents currents flowing through the first and second wires from cancelling out each other, and further enables a metallic plate to be disposed as far away from the semiconductor chip as possible. In addition, configuring the metallic plate to have a constant width that is wider than the diameters of the first and second wires results in a wide connection range, thereby ensuring connection even when mounting misalignments occur between the wires and the metallic plate.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 3, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukako Tsutsumi, Mitsuyoshi Endo, Mitsuhiro Nakao
  • Publication number: 20080231518
    Abstract: First and second wires are formed so that the further away from a semiconductor chip, the greater the distance between the first and second wires. This prevents currents flowing through the first and second wires from cancelling out each other, and further enables a metallic plate to be disposed as far away from the semiconductor chip as possible. In addition, configuring the metallic plate to have a constant width that is wider than the diameters of the first and second wires results in a wide connection range, thereby ensuring connection even when mounting misalignments occur between the wires and the metallic plate.
    Type: Application
    Filed: December 21, 2007
    Publication date: September 25, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukako Tsutsumi, Mitsuyoshi Endo, Mitsuhiro Nakao
  • Patent number: 7370412
    Abstract: An electronic device connecting method according to a first aspect of the present invention includes: mounting an electronic device having at least one electrode portion on a sheet-like porous member having a hole therein so that the electrode portion is close to the porous member; selectively irradiating a predetermined region of the porous member, on which the electronic device is mounted, with energy lines to form a latent image in an irradiated or non-irradiated portion of the porous member, the predetermined region including a portion close to the electrode portion; after irradiating with the energy lines, filling a conductive material in a hole of the latent image of the porous member to form a conductive portion; and bonding and integrating the porous member, in which the conductive portion is formed, to and with the electronic device.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Mitsuyoshi Endo, Naoko Yamaguchi, Yasuyuki Hotta, Shigeru Matake, Hideo Aoki, Misa Sawanobori
  • Patent number: 7095112
    Abstract: Provided a semiconductor device including: a wiring board; a semiconductor chip having a pad electrically connected to a wiring on the wiring board; a second semiconductor chip provided on the wiring board at a position facing a side of the semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on the wiring board electrically connected to the pad of the semiconductor chip.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: August 22, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuyoshi Endo, Mie Matsuo, Chiaki Takubo
  • Patent number: 6861738
    Abstract: There is disclosed a laminated-chip semiconductor device which comprises two chip-mounting substrates on each of which at least one semiconductor chip having a plurality of terminals for signals is mounted, and a plurality of chip connecting wirings electrically connected to the terminals for signals of the each semiconductor chip which are mounted on the chip-mounting substrates are formed in a same pattern, and which are laminated along a thickness direction, and one intermediate substrate which is arranged between the two chip-mounting substrates, and in which a plurality of interlayer connecting wirings electrically connected to each of the plurality of chip connecting wirings of the adjacent chip-mounting substrate are formed in a predetermined wiring pattern.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Oyama, Mitsuyoshi Endo, Chiaki Takubo, Takashi Yamazaki, Takashi Imoto
  • Publication number: 20040112633
    Abstract: An electronic device module comprises a wiring substrate having an insulating substrate with a porous structure including continuous pores and wiring conductors selectively formed in the porous structure; and an electronic device directly connected to said wiring conductors formed in the porous structure.
    Type: Application
    Filed: September 5, 2003
    Publication date: June 17, 2004
    Inventors: Mitsuyoshi Endo, Toshiro Hiraoka, Yasuyuki Hotta, Hideo Aoki, Hideko Mukaida, Naoko Yamaguchi
  • Publication number: 20040056341
    Abstract: Provided a semiconductor device including: a wiring board; a semiconductor chip having a pad electrically connected to a wiring on the wiring board; a second semiconductor chip provided on the wiring board at a position facing a side of the semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on the wiring board electrically connected to the pad of the semiconductor chip.
    Type: Application
    Filed: September 17, 2003
    Publication date: March 25, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mitsuyoshi Endo, Mie Matsuo, Chiaki Takubo
  • Publication number: 20040009683
    Abstract: An electronic device connecting method according to a first aspect of the present invention includes: mounting an electronic device having at least one electrode portion on a sheet-like porous member having a hole therein so that the electrode portion is close to the porous member; selectively irradiating a predetermined region of the porous member, on which the electronic device is mounted, with energy lines to form a latent image in an irradiated or non-irradiated portion of the porous member, the predetermined region including a portion close to the electrode portion; after irradiating with the energy lines, filling a conductive material in a hole of the latent image of the porous member to form a conductive portion; and bonding and integrating the porous member, in which the conductive portion is formed, to and with the electronic device.
    Type: Application
    Filed: July 3, 2003
    Publication date: January 15, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiro Hiraoka, Mitsuyoshi Endo, Naoko Yamaguchi, Yasuyuki Hotta, Shigeru Matake, Hideo Aoki, Misa Sawanobori