Abstract: A database system and a column changing method for a database are provided, where a column attribute of a first column is changed to a change target value. Second columns are added into a physical data table and a physical GSI table, and into respective structure definitions of a logical data table and a logical GSI table, and are hidden from a user. The second columns in the logical data and GSI tables are respectively associated with the second columns in the physical data and GSI tables, and a value of the attribute of the second column in the logical table is the change target value. Configuration is performed in the respective structure definitions, to replace a first column with the second column in user access logic of the database. The first columns are deleted from the physical data and GSI tables, and from the respective structure definitions.

Abstract: A laser emitting apparatus (310), a lidar (300), and a method for controlling a lidar (300) are provided, and may be applied to the field of laser technologies. The laser emitting apparatus (310) of the lidar (300) includes a first emitting module (3101) and a second emitting module (3102), a plurality of light spots generated when each emitting module emits a laser beam are discontinuous, and light spots generated when the first emitting module (3101) and the second emitting module (3102) emit laser beams alternate with each other.

Abstract: The techniques described herein relate to systems and methods for processing symbols of various types with high speed and high accuracy. The techniques can include accessing an image of a symbol comprising embedded information, inputting the image of the symbol into a deep learning module, and generating, with the deep learning module, predicted embedded information based on the image of the symbol. The predicted embedded information can include codewords, which correspond to the embedded information. The codewords can be further processed for generating the embedded information. Such techniques can enable fast and accurate processing of symbols of various types.

Abstract: A test circuit (300, 300?, 400, 500, 600, 700, 800), including: a test sequence providing module (301), configured to provide a test sequence (PRBS) to a to-be-tested sequential device (303); a clock driving module (307, 407, 507, 607, 707, 807), configured to provide a clock signal (759) to the to-be-tested sequential device (303), which includes a first clock driving circuit (610, 710), wherein the first clock driving circuit (610, 710) includes: a plurality of first clock paths (421, 423) which respectively provide corresponding clock signals (759); and a logic unit (427, 715) which generates, based on at least part of the clock signals (759) provided by the plurality of first clock paths (421, 423), a first clock signal with an adjusted pulse width, for the to-be-tested sequential device (303); and a verification module (305, 405, 805), configured to verify an output of the to-be-tested sequential device (303).

Abstract: A computing device and a computing system are provided. The computing device comprises: a plurality of computing modules; and serial communication paths between/among the plurality of computing modules. Each computing module comprises: an internal circuit for performing an operation on a signal received from a corresponding serial communication path; and an extension circuit for receiving a signal from the internal circuit as an input signal. The extension circuit comprises: a delay module for delaying the input signal, the delay module comprising one or more delay units; one or more extension select modules for selectively performing a level extension on the input signal through the signal delayed by corresponding one or more delay units to generate one or more respective level-extended signals; and an output module for outputting one or more of the one or more level-extended signals.

Abstract: Example methods and apparatus for predicting a travelable lane are described. One example method includes obtaining forward lane line information backward lane line information of a host vehicle. A first lane model is constructed based on the forward lane line information of the host vehicle. A second lane model is constructed based on the backward lane line information of the host vehicle. A first travelable lane is predicted based on the first lane model and the second lane model.

Abstract: A method of making photolithography mask plate is provided. The method includes: providing a carbon nanotube composite structure, wherein the carbon nanotube composite structure comprises a carbon nanotube layer and a chrome layer coated on the carbon nanotube layer; locating the carbon nanotube composite structure on a substrate to expose partial surfaces of the substrate; and depositing a cover layer on the carbon nanotube composite structure.

Abstract: A method of making photolithography mask plate is provided. The method includes: providing a carbon nanotube layer on a substrate; depositing a chrome layer on the carbon nanotube layer, wherein the chrome layer includes a first patterned chrome layer and a second patterned chrome layer, the first patterned chrome layer is located on the carbon nanotube layer, and the second patterned chrome layer is deposited on the substrate corresponding to holes of the carbon nanotube layer; transferring the carbon nanotube layer with the first patterned chrome layer thereon from the substrate to a base, and the carbon nanotube layer being in contact with the base; and depositing a cover layer on the first patterned chrome layer.

Abstract: A test circuit (300, 300?, 400, 500, 600, 700, 800), including: a test sequence providing module (301), configured to provide a test sequence (PRBS) to a to-be-tested sequential device (303); a clock driving module (307, 407, 507, 607, 707, 807), configured to provide a clock signal (759) to the to-be-tested sequential device (303), which includes a first clock driving circuit (610, 710), wherein the first clock driving circuit (610, 710) includes: a plurality of first clock paths (421, 423) which respectively provide corresponding clock signals (759); and a logic unit (427, 715) which generates, based on at least part of the clock signals (759) provided by the plurality of first clock paths (421, 423), a first clock signal with an adjusted pulse width, for the to-be-tested sequential device (303); and a verification module (305, 405, 805), configured to verify an output of the to-be-tested sequential device (303).

Abstract: A composition for treating TMJ degeneration comprising a hydrogel of sclerostin and high molecular weight hyaluronic acid, or PLGA-encapsulated sclerostin, or sclerostin covalently linked to hyaluronic acid.

Abstract: A method of making photolithography mask plate is provided. The method includes: providing a chrome layer on a substrate; depositing a carbon nanotube layer on the chrome layer to expose a part of a surface of the chrome layer; etching the chrome layer with the carbon nanotube layer as a mask to obtain a patterned chrome layer; and depositing a cover layer on the carbon nanotube layer.

Abstract: A computing device and a computing system are provided. The computing device comprises: a plurality of computing modules; and serial communication paths between/among the plurality of computing modules. Each computing module comprises: an internal circuit for performing an operation on a signal received from a corresponding serial communication path; and an extension circuit for receiving a signal from the internal circuit as an input signal. The extension circuit comprises: a delay module for delaying the input signal, the delay module comprising one or more delay units; one or more extension select modules for selectively performing a level extension on the input signal through the signal delayed by corresponding one or more delay units to generate one or more respective level-extended signals; and an output module for outputting one or more of the one or more level-extended signals.

Abstract: A heterogeneous processing system for federated learning and privacy-preserving computation, including: a serial subsystem configured for distributing processing tasks and configuration information of processing tasks, the processing task indicating performing an operation corresponding to computing mode on one or more operands; and a parallel subsystem configured for, based on the configuration information, selectively obtaining at least one operand of the one or more operands from an intermediate result section on the parallel subsystem while obtaining remaining operand(s) of the one or more operands with respect to the at least one operand from the serial subsystem, and performing the operation on the operands obtained based on the configuration information.

Abstract: A heterogeneous processing system for federated learning and privacy-preserving computation, including: a serial subsystem configured for distributing processing tasks and configuration information of processing tasks, the processing task indicating performing an operation corresponding to computing mode on one or more operands; and a parallel subsystem configured for, based on the configuration information, selectively obtaining at least one operand of the one or more operands from an intermediate result section on the parallel subsystem while obtaining remaining operand(s) of the one or more operands with respect to the at least one operand from the serial subsystem, and performing the operation on the operands obtained based on the configuration information.

Abstract: A shift register circuit and a method of driving the same, a gate driver circuit, an array substrate and a display device. The shift register circuit includes an input subcircuit and a signal output subcircuit. The input subcircuit includes: a control module, which is configured to output a signal of the first voltage terminal to a voltage dividing node under a control of an input signal; an input module configured to output a signal of the voltage dividing node to the signal output subcircuit under a control of the control module; and a voltage dividing module, a resistance value of the voltage dividing module having a negative relationship with a temperature, and the signal output subcircuit is connected with an output terminal of the input module and configured to output a gate scan signal from an output signal terminal under a control of the input module.

Abstract: A machine vision system that uses an imager to capture an optical image of a target object that may contain a liquid. The target object is illuminated by an illumination source positioned oppositely from the imager and a predetermined pattern is positioned between the illumination source and the target object so that the imager will capture optical images of the background pattern through any liquid positioned in the target object. A processor is programmed to analyze captured images to detect any distortions of the pattern that are attributable to the presence of a liquid in the target object.

Abstract: The present disclosure discloses a shift register, a driving method thereof, a driving circuit, and a display device. The shift register includes an input circuit, a first control circuit, a second control circuit, and an output circuit. Signal shift output can be implemented through mutual cooperation between respective circuits. An output signal can be used as a light emitting control signal of a light emitting control transistor, or can be used as a gate scanning signal of a scanning control transistor.

Abstract: The present disclosure relates to correction apparatus and correction methods. One example correction apparatus includes a first adjustment module, a plurality of second adjustment modules, a correction calculation module, and a plurality of non-ideal channels. One second adjustment module is disposed on one non-ideal channel. The first adjustment module is connected to each non-ideal channel. The correction calculation module is separately connected to the first adjustment module and the plurality of second adjustment modules. The correction calculation module is connected to an output end of each non-ideal channel. The non-ideal channel is a channel that outputs an output signal in response to a drive signal having an error value.

Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an active layer and a source/drain electrode layer which are on the base substrate. The source/drain electrode layer includes a source electrode and a drain electrode. The thin film transistor further includes a light blocking layer surrounding the active layer.

Abstract: This invention provides a composition comprising (i) a peptide having an amino acid sequence that comprises the amino acid sequence TPLSYLKGLVTV and (ii) a therapeutic agent operably affixed thereto. This invention also provides related pharmaceutical compositions, kits, and methods for treating a subject afflicted with bone cancer.