Abstract: One or more embodiments are directed to a multiport power delivery architecture that reduces the cost and maximizes the power utilization. According to some aspects, an adapter power add-up feature of the embodiments can combine the power of two or more adapters. The total power can be used to support CPU Turbo events and Quick Charge function. In one aspect, one charger operates as voltage source or current source and the other(s) as current source(s). When the system demand is high enough for all chargers may operate as current sources, the battery will supply the rest of the system demand. The proposed implementation of adapter power add-up feature can enable simple control scheme. Customers can set up BGATE control priorities to determine which charger to handle the BGATE control.

Abstract: One or more embodiments are directed to a battery charger that can support multiple battery applications with a single USB type-C port. An architecture according to one or more embodiments includes a single charger transferring power to multiple battery stacks. The architecture according or one or more embodiments includes a plurality of battery stacks each respectively housed in a distinct electronic device. The architecture according to one or more embodiments is expandable from one charger with one USB type-C port coupled to a plurality of battery stacks, to a plurality of chargers with respective USB type-C ports all coupled to a plurality of battery stacks respectively housed in distinct electronic devices.

Abstract: A shift register including an input circuit, an output circuit, a first output control circuit, a second output control circuit, a reset circuit, a first reset control circuit, a second reset control circuit, and an energy-storing circuit. The first output control circuit is configured to transfer a clock signal present at a third clock signal terminal to a first node in response to the clock signal at the third clock signal terminal being active. The second output control circuit is configured to transfer a voltage present at a first voltage terminal to the first node in response to a clock signal at a fourth clock signal terminal being active.

Abstract: Provided are a scan driving circuit and driving method thereof, array substrate and a display device. The scan driving circuit includes output ends at m stages, input circuits at m stages, and q shift register circuits. A first end of the input circuit at the i-th stage is connected to the output end at the (i?1)-th stage, and i is any integer greater than 1 and less than m+1. Any shift register circuits is respectively connected to k output ends, and second ends of k input circuits, and the k input circuits have a same combination of stage numbers as k output ends, all stage numbers in same combination of stage numbers have the same parity, and k is greater than 1 and less than m. The shift register circuit is configured to output a scanning signal to one output ends, and outputting the scanning signal to which output ends is indicated by an external control signal.

Abstract: A shift register circuit is disclosed that includes an input control circuit configured to set a first node at a first potential in response to an active pulse signal from a signal input terminal, an output control circuit configured to supply a clock signal from a first clock signal terminal to a signal output terminal in response to the first node being at the first potential, the first potential being less than a potential of the active pulse signal and greater than or equal to a potential for maintaining operation of the output control circuit, and a reset circuit configured to supply a reference voltage from a reference voltage terminal to the first node and the signal output terminal in response to a reset signal.

Abstract: A shift register including an input circuit, an output circuit, a first output control circuit, a second output control circuit, a reset circuit, a first reset control circuit, a second reset control circuit, and an energy-storing circuit. The first output control circuit is configured to transfer a clock signal present at a third clock signal terminal to a first node in response to the clock signal at the third clock signal terminal being active. The second output control circuit is configured to transfer a voltage present at a first voltage terminal to the first node in response to a clock signal at a fourth clock signal terminal being active.

Abstract: One or more embodiments are directed to a multiport power delivery architecture that reduces the cost and maximize the power utilization. According to some aspects, embodiments solve problems associated with charging a battery with multiple adapter. Some embodiments enable supplying system load and charging a battery from two or more adapters simultaneously through a single sensing resistor.

Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an active layer and a source/drain electrode layer which are on the base substrate. The source/drain electrode layer includes a source electrode and a drain electrode. The thin film transistor further includes a light blocking layer surrounding the active layer.

Abstract: A method of making a grating, the method including: providing a substrate, placing a first photoresist layer on the substrate, locating a second photoresist layer on the first photoresist layer, wherein a second exposure dose of the second photoresist layer is greater than a first exposure dose of the first photoresist layer; exposing the first photoresist layer and the second photoresist layer; developing the first photoresist layer and the second photoresist layer and removing an exposed photoresist to form a patterned photoresist layer and obtain an exposed surface of the substrate, wherein the patterned photoresist layer defines a plurality of top surfaces and a plurality of side surfaces, each adjacent top surface and side surface, and the exposed surface form a Z-type surface; depositing a preformed layer on the Z-type surface to form a Z-type structure; removing the patterned photoresist layer.

Abstract: A display substrate, a display device and a method for driving the same are provided. The display substrate includes a plurality of sub-regions. At least one subpixel unit, a common electrode voltage input line, a common electrode voltage control line and at least one control TFT are arranged at each sub-region. At each sub-region, a gate electrode of the control TFT is coupled to the common electrode voltage control line, a source electrode of the control TFT is coupled to the common electrode voltage input line, and a drain electrode of the control TFT is coupled to a common electrode of the subpixel unit.

Abstract: A method of making microstructures, including: setting a photoresist layer on a surface of a base; covering a surface of the photoresist layer with a photolithography mask plate, wherein the photolithography mask plate includes: a substrate; a patterned chrome layer on a surface of the substrate; a carbon nanotube layer on the patterned chrome layer, wherein a first pattern of the patterned chrome layer is the same as a second pattern of the carbon nanotube layer; a cover layer on the carbon nanotube layer; exposing the photoresist layer to form an exposed photoresist layer by irradiating the photoresist layer through the photolithography mask plate with ultraviolet light; and developing the exposed photoresist layer to obtain a patterned photoresist microstructures.

Abstract: A method of making microstructures, including: setting a photoresist layer on a base; covering the photoresist layer with a photolithography mask plate, wherein the photolithography mask plate includes: a substrate; a carbon nanotube layer on the substrate; a patterned chrome layer on the carbon nanotube layer so that the carbon nanotube layer is sandwiched between the patterned chrome layer and the substrate, wherein a first pattern of the patterned chrome layer is the same as a second pattern of the carbon nanotube layer; a cover layer on the patterned chrome layer; exposing the photoresist layer to form an exposed photoresist layer by irradiating the photoresist layer through the photolithography mask plate with ultraviolet light; and developing the exposed photoresist layer to obtain a patterned photoresist microstructures.

Abstract: A method of making microstructures, including: setting a photoresist layer on a surface of a base; covering a surface of the photoresist layer with a photolithography mask plate, wherein the photolithography mask plate includes: a substrate; a carbon nanotube composite structure on a surface of the substrate, wherein the carbon nanotube composite structure includes a carbon nanotube layer and a chrome layer coated on the carbon nanotube layer; and a cover layer on the carbon nanotube composite structure; exposing the photoresist layer to form an exposed photoresist layer by irradiating the photoresist layer through the photolithography mask plate with ultraviolet light; and developing the exposed photoresist layer to obtain a patterned photoresist microstructures.

Abstract: The present disclosure relates to correction apparatus and correction methods. One example correction apparatus includes a first adjustment module, a plurality of second adjustment modules, a correction calculation module, and a plurality of non-ideal channels. One second adjustment module is disposed on one non-ideal channel. The first adjustment module is connected to each non-ideal channel. The correction calculation module is separately connected to the first adjustment module and the plurality of second adjustment modules. The correction calculation module is connected to an output end of each non-ideal channel. The non-ideal channel is a channel that outputs an output signal in response to a drive signal having an error value.

Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an active layer and a source/drain electrode layer which are on the base substrate. The source/drain electrode layer includes a source electrode and a drain electrode. The thin film transistor further includes a light blocking layer surrounding the active layer.

Abstract: A method of making nanoscale channels including: providing a substrate, locating a photoresist mask layer on the substrate, the thickness of the photoresist mask layer equals H; forming a patterned mask layer by exposing and developing the photoresist mask layer, the patterned mask layer includes a plurality of parallel and spaced stripe masks, the spacing between adjacent stripe masks equals L; depositing a first thin film layer on the substrate in a first direction, the thickness of the first thin film layer equals D, a first angle between the first direction and a direction in the thickness of the stripe masks equals ?1, ?1<tan?1(L/H); depositing a second thin film layer on the substrate in a second direction, a second angle between the second direction and the direction in the thickness of the stripe masks equals ?2, ?2<tan?1[L/(H+D)], 0<Htan?1+(H+D)tan?2?L<10 nm.

Abstract: A method of making thin film transistor including: forming a gate electrode, forming a gate insulating layer on the gate electrode; locating a semiconductor layer on the gate insulating layer; placing stripe-shaped masks on the semiconductor layer, wherein the thickness of the stripe-shaped masks is H, the spacing distance between the stripe-shaped masks is L; depositing a first conductive film layer along a first direction, the thickness of the first conductive film layer is D, a first angle between the first direction and a direction along the thickness of the stripe-shaped masks is ?1, ?1<tan?1(L/H); depositing a second conductive film layer along a second direction, a second angle between the second direction and the direction along the thickness of the stripe-shaped masks is ?2, ?2<tan?1[L/(H+D)], 0<Htan?1+(H+D)tan?2?L<10 nm, the first conductive film layer forms a source electrode, the second conductive film layer forms a drain electrode.

Abstract: A photolithography mask plate, the photolithography mask plate including: a substrate; a carbon nanotube composite structure on a surface of the substrate, wherein the carbon nanotube composite structure comprises a carbon nanotube layer and a chrome layer coated on the carbon nanotube layer; a cover layer on the carbon nanotube composite structure.

Abstract: A display substrate and a display device are disclosed. The display substrate includes an active area and a non-active area, and an afterimage removing device for adsorbing charged ions by forming a potential difference is provided in the non-active area.