Abstract: The present embodiments are directed to an improved switched capacitor (SC) converter topology that does not include an inductor. In particular, the topology includes a ladder SC circuit configured as a cap divider, with a gate driving signal being generated to initiate the charging and discharging of the capacitor. In this specific topology, an unregulated output voltage is produced that is a certain fraction of an input voltage of a power source such as a battery. The present embodiments further include a variable frequency modulation (VFM) scheme based on the current-sensing techniques for the gate driving signal generation of the switched capacitor converter.

Abstract: The present embodiments are directed to an improved switched capacitor (SC) converter topology that does not include an inductor. In particular, the topology includes a ladder SC circuit configured as a cap divider, with a gate driving signal being generated to initiate the charging and discharging of the capacitor. In this specific topology, an unregulated output voltage is produced that is a certain fraction of an input voltage of a power source such as a battery. The present embodiments further include a variable frequency modulation (VFM) scheme based on the current-sensing techniques for the gate driving signal generation of the switched capacitor converter.

Abstract: The present embodiments relate generally to switched-capacitor (SC) based DC-DC converters, and more particularly to modulation schemes of cap dividers that include ceramic capacitors such as MLCCs. According to certain general aspects, the present embodiments increase the switching frequency at light loads using variable frequency modulation schemes to reduce the voltage difference across the MLCCs. In these and other embodiments, the acoustic noise generated from the MLCCs can be reduced while maintaining excellent light load efficiency. According to certain aspects, this can be achieved with minimal impact on system performance, cost and size.

Abstract: A shift register includes a first input circuit, a second input circuit, and a pull-up transistor. The first input circuit is coupled to a first input terminal and a first pull-up node, and configured to electrically connect the first input terminal to the first pull-up node when the first input terminal receives an active signal. The second input circuit is coupled to a second input terminal and a second pull-up node, and configured to electrically connect the second input terminal to the second pull-up node when the second input terminal receives an active signal. The pull-up transistor includes a first gate electrode coupled to the first pull-up node and a second gate electrode coupled to the second pull-up node.

Abstract: A method of making nano-scaled channel, the method including: locating a first photoresist layer, a nanowire structure, and a second photoresist layer on a surface of a substrate, and the nanowire structure being sandwiched between the first photoresist layer and the second photoresist layer, wherein the nanowire structure comprises an nanowire; forming an opening in the first photoresist layer and the second photoresist layer to expose a portion of the surface of the substrate to form an exposed surface, wherein a part of the nanowire is exposed and suspended in the opening, and both ends of the nanowire are sandwiched between the first photoresist layer and the second photoresist layer; and depositing a thin film layer on the exposed surface of the substrate using the a nanowire as a mask, wherein the thin film layer defines a nano-scaled channel corresponding to the at least one nanowire.

Abstract: A method of making a thin film transistor, the method including: providing an insulating layer on a semiconductor substrate, forming a semiconductor layer on the insulating layer; locating a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, wherein the nanowire structure comprises a nanowire; forming an opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed in the opening; depositing a conductive film layer on the exposed surface of the semiconductor layer, wherein the conductive film layer defines a nano-scaled channel corresponding to the nanowire, and the conductive film layer is divided into two regions by the nano-scaled channel, one region is used as a source electrode, and the other region is used as a drain electrode; forming a gate electrode on the semiconductor substrate.

Abstract: A method of making nanostructures including: locating a photoresist mask layer on a substrate, the thickness of the photoresist mask layer is H; forming a patterned mask layer includes a plurality of stripe masks, a spacing distance between adjacent stripe masks equals L; depositing a first thin film layer along a first direction, the thickness of the first thin film layer is D, a first angle between the first direction and a direction along the thickness of stripe masks is ?1, ?1<tan?1(L/H); depositing a second thin film layer along a second direction, a second angle between the second direction and the direction along the thickness of stripe masks is ?2, ?2<tan?1[L/(H+D)], 0<L?H tan ?1?(H+D)tan?2<10 nm, the first thin film layer partly overlaps with the second thin film layer to form an overlapping structure; etching the first thin film layer and the second thin film layer to obtain a nanoscale microstructure.

Abstract: A Mura compensation circuit and method, a driving circuit and a display device are provided. The Mura compensation circuit comprises: a vertical Mura compensation unit, for providing a corresponding gamma voltage to a vertical block Mura region and a vertical non-Mura region of a display panel respectively, to compensate for a vertical Mura phenomenon; and/or a horizontal Mura compensation unit, for providing a corresponding gate drive signal and/or a corresponding charging/discharging control signal to a horizontal block Mura region and a horizontal non-Mura region of a display panel respectively, to compensate for a horizontal Mura phenomenon. The Mura compensation circuit can make the different regions of the display panel have the same display effect, and improve reduction of display quality caused by impedance difference at different positions of the display panel, thereby raising the quality of a picture, and can be promoted and applied widely.

Abstract: A method of making a thin film transistor, the method includes: providing a semiconductor layer; arranging a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, wherein the nanowire structure includes a single nanowire; forming one opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed and suspended in the opening; depositing a conductive film layer on the exposed surface using the nanowire structure as a mask, wherein the conductive film layer defines a nano-scaled channel, and the conductive film layer is divided into two regions, one region is used as a source electrode, and the other region is used as a drain electrode; forming an insulating layer on the semiconductor layer to cover the source electrode and the drain electrode, and locating a gate electrode on the insulating layer.

Abstract: A method of making microstructures, the method including: providing a first substrate, setting a photoresist layer on a surface of the first substrate; covering a surface of the photoresist layer with a photolithography mask plate, wherein the photolithography mask plate comprises a second substrate and a carbon nanotube composite layer located on a surface of the second substrate; exposing the photoresist layer to form an exposed photoresist layer by irradiating the photoresist layer through the photolithography mask plate with ultraviolet light; developing the exposed photoresist layer to obtain a patterned photoresist microstructures.

Abstract: The present disclosure provides a pixel driver circuit, a pixel circuit, a display panel and a display device. The pixel driver circuit includes two pixel driving units having an identical structure. Each pixel driving unit includes a driving transistor and a driving control module. A gate electrode of the driving transistor is connected to the driving control module, a first electrode thereof receives a first power voltage, and a second electrode thereof is connected to the driving control module and a light-emitting element. The driving control module is connected to a data line, a gate line, and the gate electrode and the second electrode of the driving transistor, and controls a potential at the gate electrode of the driving transistor in accordance with a data voltage applied to the data line under control of a gate driving signal from the gate line, so as to turn on/off the driving transistor.

Abstract: A method of making a thin film transistor, the method including: forming a gate insulating layer on a gate electrode; placing a semiconductor layer on the gate insulating layer; locating a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, the nanowire structure being sandwiched between the first photoresist layer and the second photoresist layer, wherein the nanowire structure comprises one nanowire; forming one opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed in the opening; depositing a conductive film layer on the exposed surface of the semiconductor layer, wherein the conductive film layer defines a nano-scaled channel corresponding to the nanowire, the conductive film layer is divided into two regions, one region is used as a source electrode, the other region is used as a drain electrode.

Abstract: The present disclosure provides a gate driving circuit, a method for detecting the gate driving circuit, an array substrate and a display apparatus. The gate driving circuit comprises a plurality of cascaded gate driving units, access units, a first signal line and a second signal line. Each access unit is connected to its corresponding gate driving unit and the gate driving unit at the next stage to its corresponding gate driving unit. The access unit corresponding to the gate driving unit at each odd stage is connected to the first signal line such that the first signal line detects an output signal from that gate driving unit via the access unit, and the access unit corresponding to the gate driving unit at each even stage is connected to the second signal line such that the second signal line detects an output signal from that gate driving unit via the access unit.

Abstract: A shift register includes a first input circuit, a second input circuit, and a pull-up transistor. The first input circuit is coupled to a first input terminal and a first pull-up node, and configured to electrically connect the first input terminal to the first pull-up node when the first input terminal receives an active signal. The second input circuit is coupled to a second input terminal and a second pull-up node, and configured to electrically connect the second input terminal to the second pull-up node when the second input terminal receives an active signal. The pull-up transistor includes a first gate electrode coupled to the first pull-up node and a second gate electrode coupled to the second pull-up node.

Abstract: A shift register circuit includes a set circuit, a first reset circuit, a first control circuit, and an output circuit. The output circuit is configured to change an active potential at the first node further away from an inactive potential in response to a first clock signal transferred to a signal output terminal being active, and the first control circuit is further configured to, responsive to the first clock signal transferred to the signal output terminal being active, restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage, the second reference voltage having a magnitude between an active input pulse and the inactive potential.

Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an active layer and a source/drain electrode layer which are on the base substrate. The source/drain electrode layer includes a source electrode and a drain electrode. The thin film transistor further includes a light blocking layer surrounding the active layer.

Abstract: The embodiments of the present disclosure provide a shift register, a gate driving circuit and a display apparatus. The shift register comprises an input unit, a first reset unit, a node control unit, a gate-shaping unit, a first output unit and a second output unit. The shift register is configured to change a potential of a scan signal outputted from a driving signal output terminal, so as to produce a scan signal having a gate-shaped waveform.

Abstract: The present disclosure provides a shift register unit, which includes an input circuit, a reset circuit, a noise reduction circuit, and an output circuit. The input circuit is configured to control a voltage of a first node based on a first input signal and a second input signal, and control a voltage of a second node based on a first voltage and the voltage of the first node. The reset circuit is configured to reset the voltage of the first node and the voltage of the second node. The noise reduction circuit is configured to maintain a reset voltage of the first node and a reset voltage of the second node. The output circuit is configured to provide, for an output terminal of the output circuit, a second clock signal from a second clock signal terminal or the second voltage. The shift register unit is composed of switch elements.

Abstract: The present disclosure provides a shift register unit, which includes an input circuit, a reset circuit, a noise reduction circuit, and an output circuit. The input circuit is configured to control a voltage of a first node based on a first input signal and a second input signal, and control a voltage of a second node based on a first voltage and the voltage of the first node. The reset circuit is configured to reset the voltage of the first node and the voltage of the second node. The noise reduction circuit is configured to maintain a reset voltage of the first node and a reset voltage of the second node. The output circuit is configured to provide, for an output terminal of the output circuit, a second clock signal from a second clock signal terminal or the second voltage. The shift register unit is composed of switch elements.

Abstract: A shift register circuit is disclosed that includes an input control circuit configured to set a first node at a first potential in response to an active pulse signal from a signal input terminal, an output control circuit configured to supply a clock signal from a first clock signal terminal to a signal output terminal in response to the first node being at the first potential, the first potential being less than a potential of the active pulse signal and greater than or equal to a potential for maintaining operation of the output control circuit, and a reset circuit configured to supply a reference voltage from a reference voltage terminal to the first node and the signal output terminal in response to a reset signal.