Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.

Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.

Abstract: A semiconductor device (10,50) is disclosed which can accommodate a negative voltage on its source using a P-type substrate (12) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as well as a negative voltage applied to the source. A drain contact region (29) is recessed by a dimension (X) from a first insulated region (18). The dimension (X) provides for an optimum distance for high voltage applications while avoiding lateral surface punch-through. A second embodiment illustrates a gate structure (52) having a shape which surrounds a drain contact region (62) and accommodates a high voltage application while also eliminating the lateral surface punch-through. The drain contact region (62) is formed in a P-type region (20) centered inside the gate structure (52).

Abstract: A semiconductor device (10,50) is disclosed which can accommodate a negative voltage on its source using a P-type substrate (12) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as well as a negative voltage applied to the source. A drain contact region (29) is recessed by a dimension (X) from a first insulated region (18). The dimension (X) provides for an optimum distance for high voltage applications while avoiding lateral surface punch-through. A second embodiment illustrates a gate structure (52) having a shape which surrounds a drain contact region (62) and accommodates a high voltage application while also eliminating the lateral surface punch-through. The drain contact region (62) is formed in a P-type region (20) centered inside the gate structure (52).

Abstract: A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion and merge together into a single channel region. The resulting channel region has a dopant concentration that is less than the dopant concentrations of the individual HV regions. The compact MOS device exhibits a low threshold voltage characteristic.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate (105). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the “on” state.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with a top layer (108) of opposite conductivity. The doping in the top layer (108) varies laterally, increasing breakdown voltage and decreasing on-resistance.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with a top layer (108) of opposite conductivity. A thin layer of oxide (124) is formed over the top layer (108).

Abstract: A high voltage MOS device (100) with multiple p-regions (110) is disclosed. The device comprises a plurality of p-regions (110) arranged as multiple segments both perpendicular to and parallel to current flow. The p-regions (110) allow for depletion in all directions when the device is blocking voltage, leading to a high breakdown voltage. During operation, the multiple regions have multiple conductivity channels (118) of high conductivity that allows current to flow, thus enhancing on-resistance.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate (105). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the “on” state.

Abstract: A high voltage device (100) is provided that has distinct field oxide regions (122) surrounded by p-top regions (108). The device is formed by first forming a p-top region (108) and then forming a patterned field oxide layer (122) over the p-top region (108). The field oxide layer (122) has open areas where the p-top region (108) is not covered by field oxide (122). The field oxide layer (122) that overlies the p-top region (108) consumes the p-top region (108) leaving exposed p-top regions (108) between the field oxide layer (122). Alternatively, the device (100) is formed by first forming a pattern of field oxide (122) on top of the device (100). Then, an implantation step is performed to form a p-top region (108). The areas of field oxide (122) block the implant. The areas where there are openings allow the formation of p-top regions (108) between the field oxide (122).