Patents by Inventor Mohan J. Kumar

Mohan J. Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190068521
    Abstract: Technologies for congestion management include multiple storage sleds, compute sleds, and other computing devices in communication with a resource manager server. The resource manager server discovers the topology of the sleds and one or more layers of network switches that connect the sleds. The resource manager server constructs a model of network connectivity between the sleds and the switches based on the topology, and determines an oversubscription of the network based on the model. The oversubscription is based on available bandwidth for the layer of switches and maximum potential bandwidth used by the sleds. The resource manager server determines bandwidth limits for each sled and programs each sled with the corresponding bandwidth limit. Each sled enforces the programmed bandwidth limit. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 28, 2019
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Publication number: 20190042511
    Abstract: An apparatus is described. The apparatus includes a non volatile memory module for insertion into a rack implemented modular computer. The non volatile memory module includes a plurality of memory controllers. The non volatile memory includes respective non-volatile random access memory coupled to each of the memory controllers. The non volatile memory module includes a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers. The incoming requests are sent by one or more CPU modules of the rack implemented modular computer. The outgoing responses are sent to the one or more CPU modules.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Inventors: Murugasamy K. NACHIMUTHU, Mark A. SCHMISSEUR, Dimitrios ZIAKAS, Debendra DAS SHARMA, Mohan J. KUMAR
  • Publication number: 20190042089
    Abstract: Examples include techniques for determining a storage policy for storing data in a computing system having one or more storage nodes, each storage node including one or more storage devices. One technique includes getting rating information from a storage device of a storage node; assigning the storage device to a storage pool based at least in part on the rating information; and automatically determining a storage policy for the computing system based at least in part on the assigned storage pool and the rating information.
    Type: Application
    Filed: March 2, 2018
    Publication date: February 7, 2019
    Inventors: Anjaneya R. CHAGAM REDDY, Mohan J. KUMAR, Sujoy SEN, Murugasamy K. NACHIMUTHU, Gamil CAIN
  • Publication number: 20190042136
    Abstract: Technologies for dividing resources across partitions include a compute sled. The compute sled is to determine partitions among sockets of the compute sled. Each socket is associated with a corresponding processor. The compute sled is also to establish a separate memory space for each determined partition, obtain, from an application executed in one of the sockets, a request to access a logical memory address, identify the partition associated with the memory access request, determine a corresponding physical memory address as a function of the identified partition and the logical memory address, and access a memory of the compute sled at the determined physical memory address. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 7, 2019
    Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar
  • Publication number: 20190042440
    Abstract: A method performed by a first hardware element in a hierarchical arrangement of hardware elements in an object storage system is described. The method includes performing a hash on a name of an object of the object storage system. The name is part of a request that is associated with the object. A result of the hash is to identify a second hardware element directly beneath the first hardware element in the hierarchical arrangement. The request is to be sent to the second hardware element to advance the request toward being serviced by the object storage system.
    Type: Application
    Filed: March 29, 2018
    Publication date: February 7, 2019
    Inventors: Mohan J. KUMAR, Anjaneya R. CHAGAM REDDY
  • Publication number: 20190042308
    Abstract: Technologies for providing efficient scheduling of functions include a compute device. The compute device is configured to obtain a function dependency graph indicative of data dependencies between functions to be executed in a networked set of compute devices, perform a cluster analysis of the execution of the functions in the networked set of compute devices to identify additional data dependencies between the functions, and update, based on the cluster analysis, the function dependency graph.
    Type: Application
    Filed: August 31, 2018
    Publication date: February 7, 2019
    Inventors: Mohan J. Kumar, Krishna Bhuyan
  • Publication number: 20190042277
    Abstract: Technologies for utilizing a runtime code present in an option read only memory (ROM) include a sled that includes a device having an option ROM with runtime code indicative of a runtime function of the device. The sled is to detect, in a boot process, the device on the sled, access, in the boot process, the runtime code in the option ROM of the detected device to identify the runtime function, and execute, in a runtime process, the runtime function associated with the runtime code. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 7, 2019
    Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar
  • Publication number: 20190044849
    Abstract: Technologies for load balancing a storage network include a system. The system includes circuitry to adjust routing rules in a network interface controller to deliver a packet from one of multiple uplinks to one of any physical functions, circuitry to remap, in response to a failure of a switch, a port from one physical function to another physical function, and circuitry to communicate control data between a software defined network controller and one or more agents in one or more host endpoints with a hierarchical distributed hashing table.
    Type: Application
    Filed: July 25, 2018
    Publication date: February 7, 2019
    Inventors: Mrittika Ganguli, Yadong Li, Michael Orr, Anjaneya Reddy Chagam Reddy, Mohan J. Kumar
  • Publication number: 20190042144
    Abstract: Examples include methods for obtaining one or more location hints applicable to a range of logical block addresses of a received input/output (I/O) request for a storage subsystem coupled with a host system over a non-volatile memory express over fabric (NVMe-oF) interconnect. The following steps are performed for each logical block address in the I/O request. A most specific location hint of the one or more location hints that matches that logical block address is applied to identify a destination in the storage subsystem for the I/O request. When the most specific location hint is a consistent hash hint, the consistent hash hint is processed. The I/O request is forwarded to the destination and a completion status for the I/O request is returned. When a location hint log page has changed, the location hint log page is processed. When any location hint refers to NVMe-oF qualified names not included in the immediately preceding query by the discovery service, the immediately preceding query is processed again.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 7, 2019
    Inventors: Scott D. PETERSON, Sujoy SEN, Anjaneya R. CHAGAM REDDY, Murugasamy K. NACHIMUTHU, Mohan J. KUMAR
  • Patent number: 10185619
    Abstract: An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Theodros Yigzaw, Ashok Raj, Robert Swanson, Mohan J. Kumar
  • Patent number: 10176108
    Abstract: Provided are a method, apparatus, and a system in which an initiator node is configured to communicate with a target node that is coupled to a memory. At system initialization time, a memory address map of the initiator node is generated to include addresses corresponding to the memory to which the target node is coupled. The initiator node accesses the memory coupled to the target node, by using the memory address map of the initiator node.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 8, 2019
    Assignee: INTEL CORPORATION
    Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar, Dimitrios Ziakas
  • Publication number: 20190004894
    Abstract: Apparatuses, systems and methods are disclosed herein that generally relate to distributed network storage and filesystems, such as Ceph, Hadoop®, or other big data storage environments utilizing resources and/or storage that may be remotely located across a communication link such as a network. More particularly, disclosed are techniques for one or more machines or devices to scrub data on remote resources and/or storage without requiring all or substantially all of the remote data to be read across the communication link in order to scrub it. Some disclosed embodiments discuss having validation be relatively local to storage(s) being scrubbed, and some embodiments discuss only providing to the one or more machines scrubbing data selected results of the relatively local scrubbing over the communication link.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Anjaneya R. Chagam Reddy, Mohan J. Kumar, Sujoy Sen, Tushar Gohad
  • Patent number: 10169268
    Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Mahesh Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
  • Patent number: 10162761
    Abstract: An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Ashok Raj, Sreenivas Mandava, Sarathy Jayakumar, Mohan J Kumar, Theodros Yigzaw, Ronald N Story
  • Publication number: 20180337991
    Abstract: Non-volatile Memory Express over Fabric (NVMeOF) using Volume Management Device (VMD) schemes and associated methods, systems and software. The schemes are implemented in a data center environment including compute resources in compute drawers and storage resources residing in pooled storage drawers that are communicatively couple via a fabric. Compute resources are composed as compute nodes or virtual machines/containers running on compute nodes to utilize remote storage devices in pooled storage drawers, while exposing the remote storage devices as local NVMe storage devices to software running on the compute nodes. This is facilitated by virtualizing the system's storage infrastructure through use of hardware-based components, firmware-based components, or a combination of hardware/firmware- and software-based components. The schemes support the use of remote NVMe storage devices using an NVMeOF protocol and/or use of non-NVMe storage devices using NVMe emulation.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Applicant: Intel Corporation
    Inventors: MOHAN J. KUMAR, MURUGASAMY K. NACHIMUTHU
  • Publication number: 20180324052
    Abstract: Trusted platform telemetry mechanisms and associated methods, apparatus, and firmware components. Trusted telemetry mechanisms are provided for securely collecting platform telemetry data from telemetry data sources on a compute platform, such as machine specific registers (MSRs), device registers, system management bus (SMBus) and memory controllers. The telemetry data is collected from the telemetry data sources using various mechanisms, and securely stored on the compute platform in a manner that is inaccessible to software running on the compute platform. A submission queue and completion queue model may also be implemented to facilitate collection of telemetry data. In addition, a memory-mapped input-output (MMIO) aliasing scheme is provided to facilitate collection of telemetry data from platform telemetry data sources using various access mechanisms.
    Type: Application
    Filed: May 3, 2017
    Publication date: November 8, 2018
    Applicant: Intel Corporation
    Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar
  • Patent number: 10116750
    Abstract: Methods and apparatus for highly available rack management in Rack Scale environment. Rack Management Modules (RMMs) are configured to manage power and thermal zones in a rack including a plurality of pooled system drawers, wherein each pooled system drawer is associated with a respective power zone including power sensors and power control devices and a respective thermal zone including thermal sensors and thermal devices. During operation, one of the RMMs is implemented as a master RMM, and the other is implemented as a slave RMM. The master RMM is used to monitor the power and thermal zones. State information is periodically synchronized between the master RMM and the slave RMM. The RMMs are further configured to perform a fail-over operation in connection with a failed or failing RMM, where after the fail-over operation the slave becomes the new master RMM and the previous master RMM becomes the new slave.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Patent number: 10116518
    Abstract: Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Ramamurthy Krithivas, Narayan Ranganathan, Mohan J. Kumar, John C. Leung
  • Patent number: 10110671
    Abstract: A method, system, and device for managing hardware resources in a cloud scheduling environment includes a zone controller. The zone controller can manage groups of node servers in a cloud datacenter using a checkin service. The checkin service allows server groups to be created automatically based on one or more hardware characteristics of the node servers, server health information, workload scheduling or facilities management parameters, and/or other criteria.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Mrittika Ganguli, Mohan J. Kumar, Deepak S, Jaiber J. John
  • Publication number: 20180288152
    Abstract: Apparatus and method for storage accessibility are disclosed herein. In some embodiments, a compute node may include one or more memories; and one or more processors in communication with the one or more memories, wherein the one or more processors include a module that is to select one or more particular storage devices of a plurality of storage devices distributed over the network in response to a data request made by an application that executes on the one or more processors, the one or more particular storage devices selected to fulfill the data request, and the module selects the one or more particular storage devices in accordance with a data object associated with the data request and one or more of current hardware operational state of respective storage devices of the plurality of storage devices and current performance characteristics of the respective storage devices of the plurality of storage devices.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: ANJANEYA R. CHAGAM REDDY, Mohan J. Kumar, Tushar Gohad