Abstract: Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer.

Abstract: A translated wafer stand-in tester (TWST), being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The TWST may include several stacked and attached layers, at least one internal layer including electronic components operable to interact with a test system.

Abstract: An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs.

Abstract: An apparatus for providing electrical pathways between one or more unsingulated integrated circuits and one or more test circuits external to the integrated circuits, includes a flexible substrate having a first major surface and a second major surface, a plurality of first contact structures disposed in a central portion of the first surface of the flexible substrate, a plurality of second contact structures disposed in a peripheral annular region of the first surface of the flexible substrate, and a plurality of first electrically conductive pathways, each of the plurality of first electrically conductive pathways coupled to a respective first and second contact structure, wherein the second surface is free from first contact structures, second contact structures, and first electrically conductive pathways.

Abstract: Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer.

Abstract: A low-cost alignment system suitable for aligning a wafer to a test fixture includes a bundle of optical fibers wherein at least one fiber serves to deliver illumination to the alignment target from an end thereof, and a plurality of receiver fibers, each having ends with a known spatial relationship to the end of the illuminator fiber. The ends of the fiber bundle have a known spatial relationship to the fixture. In some embodiments, the fiber bundle is disposed within the fixture such that there is an unobscured optical path between the wafer and the receiving and illuminating ends of the fibers. In some embodiments, the fiber bundle is coupled to a light source and a light sensor mounted on the fixture. In some embodiments the alignment target is one or more bonding pads disposed on a wafer.

Abstract: Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer.

Abstract: Application of a conductive material with a compliant underlayer onto selected pads of a substrate, includes forming at least one padstack, by patterning a sheet including a stack of material layers. Padstacks may include a first conductive top layer, one or more underlying layers, and a bottom attachment layer, such as a solder layer. At least one flexible, or compliant, layer is disposed in the sheet between the top and attachment layers. The compliant layer may be a conductive elastomer. The top layer of the padstacks are adhered to a soluble tape, and this composite structure is moved into place over the circuit board by means of a pick and place operation. The placement of the padstacks is followed by a solder reflow to adhere the padstacks to the contact pads of the substrate, and by a wash cycle with a solvent to remove the soluble tape.

Abstract: Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate.

Abstract: A low-cost alignment system suitable for aligning a wafer to a test fixture includes a bundle of optical fibers wherein at least one fiber serves to deliver illumination to the alignment target from an end thereof, and a plurality of receiver fibers, each having ends with a known spatial relationship to the end of the illuminator fiber. The ends of the fiber bundle have a known spatial relationship to the fixture. In some embodiments, the fiber bundle is disposed within the fixture such that there is an unobscured optical path between the wafer and the receiving and illuminating ends of the fibers. In some embodiments, the fiber bundle is coupled to a light source and a light sensor mounted on the fixture. In some embodiments the alignment target is one or more bonding pads disposed on a wafer.

Abstract: A flexible extension wafer translator includes a wafer translator portion, one or more flexible connectors extending outwardly therefrom, and a connector tab coupled to the distal end of each outwardly extending flexible connector. The flexible connectors may take any suitable form, including but not limited to, draped and pleated.

Abstract: A metallization pattern for a wafer translator provides a high density layout of interdigitated contact pads, suitable for component placement, along with larger contact pads suitable for connection to external equipment terminals. In another aspect, electrically conductive material may be added to, or removed from, the high density layout of interdigitated contact pads and larger contact pads to modify, or reconfigure, the electrical pathways of the wafer translator.

Abstract: Methods and apparatus for producing fully tested unsingulated integrated circuits without probe scrub damage to bond pads includes forming a wafer/wafer translator pair removably attached to each other wherein the wafer translator includes contact structures formed from a soft crushable electrically conductive material and these contact structures are brought into contact with the bond pads in the presence of an inert gas; and subsequently a vacuum is drawn between the wafer and the wafer translator. In one aspect of the present invention, the unsingulated integrated circuits are exercised by a plurality of test systems wherein the bond pads are never physically touched by the test system and electrical access to the wafer is only provided through the inquiry-side of the wafer translator. In a further aspect of the present invention, known good die having bond pads without probe scrub marks are provided for incorporation into products.

Abstract: A translated wafer stand-in tester (TWST), being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The TWST may include several stacked and attached layers,, at least one internal layer including electronic components operable to interact with a test system.

Abstract: A low-cost alignment system suitable for aligning a wafer to a test fixture includes a bundle of optical fibers wherein at least one fiber serves to deliver illumination to the alignment target from an end thereof, and a plurality of receiver fibers, each having ends with a known spatial relationship to the end of the illuminator fiber. The ends of the fiber bundle have a known spatial relationship to the fixture. In some embodiments, the fiber bundle is disposed within the fixture such that there is an unobscured optical path between the wafer and the receiving and illuminating ends of the fibers. In some embodiments, the fiber bundle is coupled to a light source and a light sensor mounted on the fixture. In some embodiments the alignment target is one or more bonding pads disposed on a wafer.

Abstract: Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer.

Abstract: A replacement for probe cards includes a full wafer contacter. A first surface of the full wafer contacter is brought into contact with, and the contacter is attached to, a wafer, thereby making electrical connection with at least a portion of the contact pads on each of a plurality of integrated circuits on the wafer. The full wafer contacter provides conductive pathways from the IC contact pads to a second surface of the full wafer contacter where a corresponding set of contact pads provide access to test systems and/or other devices. The contact pads on the second surface of the full wafer contacter are typically larger than the contact pads of the integrated circuits, and are typically spaced father apart from each other. The full wafer contacter is constructed to be suitable to provide access to the contact pads of the unsingulated integrated circuits during a wafer burn-in process.

Abstract: A small-footprint wafer analysis, or test, station, suitable for personal or desktop use, includes a chuck mounted upon a base, an x-y motion mechanism slidably attached to the base, a contact array carrier slidably attached to the x-y motion mechanism, and an optical alignment mechanism attached to the contact array carrier.

Abstract: Coax and twinax connector assemblies, suitable for low-cost manufacturing and high-frequency performance, include one or more slices of insulating material having a series of through-holes therein. Dimensions of the through-holes are tailored to the dimensions of the coax or twinax that are to be fitted to such connector assemblies. The slices may have dimensions that are uniform to within typical manufacturing tolerances. By combining, or stacking, the slices, the connector height can be customized to a particular application. A variety of slice thicknesses are provided so that a variety of final connector heights may be achieved. Conductive material sheets may be disposed between one or more pairs of connector slices so as to provide a common ground connection for one or more conductors, such as, for example, ground shields, disposed in the through-holes of the stacked connector slices. Additionally, right angle connectors and low-cost twinax cables are disclosed.

Abstract: A component for use in manufacturing circuit boards, such as printed circuit boards, or flex substrates is adapted for use with pick-and-place equipment to provide a first material overlay disposed over a second material base layer. Such a component may include a first electrically conductive material disposed over a second electrically conductive material, and a soluble tape backing disposed over and attached to the second electrically conductive material. The component may be attached to a circuit board by solder relow, after which the soluble tape backing is removed. Although typical embodiments involve electrically conductive materials, it is noted that an electrically insulating material can also be disposed over and attached to an underlying material which itself is disposed on a circuit board.