Abstract: A conductor carrier provides, separately manufactured, conductive pathways, on a wafer level, which may be coupled to a wafer of fully fabricated integrated circuits. Such conductor carriers include an insulating body having two major surfaces with conductors disposed on each of those surfaces, and conductors disposed within the insulating body so as to provide signal continuity between various conductors on each of the two surfaces. An assembly can be formed by permanently or removably attaching the conductor carrier to the wafer. Conductor carriers may include an evacuation pathway suitable for removing air, or other gases, from between the conductor and the wafer so as to create a pressure differential that urges the conductor carrier into contact with the wafer. Conductor carriers may include a groove which is suitable for receiving a sealing ring; and may include a street map which is suitable for providing guidance to a wafer sawing operation.

Abstract: A unified process of making an electrical structure includes performing a plurality of laser etching operations on a workpiece, without removing the workpiece from a laser processing system. The workpiece includes a conductive material disposed on an electrically insulating substrate, and the plurality of laser etching operations include, but are not limited to, two or more of forming a fiducial, forming thick metal traces separated by high aspect ratio spaces, cutting an alignment hole, cutting a folding line, and singulating the electrical structure. In another aspect of the invention, a database is prepared, and communicatively coupled to the laser processing system to provide control signals that direct a portion of the plurality of operations of the laser processing system, wherein each plurality of etching operations is defined with respect to a common coordinate system.

Abstract: Methods and apparatus are provided for I/O pads of unsingulated integrated circuits, to be connected to electrical equipment. A translator plate is interposed between a wafer and tester. The translator plate includes a substrate having two major opposing surfaces, each surface having terminals disposed thereon, and electrical pathways disposed through the substrate to provide for electrical continuity between at least one terminal on a first surface and at least one terminal on the second surface. The translator plate, when interposed between wafer and tester, makes electrical contact with one or more I/O pads of a plurality of integrated circuits on the wafer, providing an electrical pathway therethrough. An anisotropic conductor is disposed between the wafer and the translator plate. A vibratory mechanism, oriented to provide substantially horizontal vibratory motion to the wafer, may be coupled to the wafer to assist disposing the translator plate and anisotropic conductor over the wafer.

Abstract: Reduced impedance mismatches are obtained when coupling electrical signalling media by replacing conventional connector architectures, which disrupt transmission line characteristics, with an electrical coupling means that permits the electrical signalling media to present a planar interface for interconnection.

Abstract: A unified process of making an electrical structure includes performing a plurality of laser etching operations on a workpiece, without removing the workpiece from a laser processing system. The workpiece includes a conductive material disposed on an electrically insulating substrate, and the plurality of laser etching operations include, but are not limited to, two or more of forming a fiducial, forming thick metal traces separated by high aspect ratio spaces, cutting an alignment hole, cutting a folding line, and singulating the electrical structure. In another aspect of the invention, a database is prepared, and communicatively coupled to the laser processing system to provide control signals that direct a portion of the plurality of operations of the laser processing system, wherein each plurality of etching operations is defined with respect to a common coordinate system.

Abstract: Coax and twinax connector assemblies, suitable for low-cost manufacturing and high-frequency performance, include one or more slices of insulating material having a series of through-holes therein. Dimensions of the through-holes are tailored to the dimensions of the coax or twinax that are to be fitted to such connector assemblies. The slices may have dimensions that are uniform to within typical manufacturing tolerances. By combining, or stacking, the slices, the connector height can be customized to a particular application. A variety of slice thicknesses are provided so that a variety of final connector heights may be achieved. Conductive material sheets may be disposed between one or more pairs of connector slices so as to provide a common ground connection for one or more conductors, such as, for example, ground shields, disposed in the through-holes of the stacked connector slices. Additionally, right angle connectors and low-cost twinax cables are disclosed.

Abstract: A replacement for probe cards includes a full wafer contacter. A first surface of the full wafer contacter is brought into contact with, and the contacter is attached to, a wafer, thereby making electrical connection with at least a portion of the contact pads on each of a plurality of integrated circuits on the wafer. The full wafer contacter provides conductive pathways from the IC contact pads to a second surface of the full wafer contacter where a corresponding set of contact pads provide access to test systems and/or other devices. The contact pads on the second surface of the full wafer contacter are typically larger than the contact pads of the integrated circuits, and are typically spaced father apart from each other. The full wafer contacter is constructed to be suitable to provide access to the contact pads of the unsingulated integrated circuits during a wafer burn-in process.

Abstract: A conductor carrier provides, separately manufactured, conductive pathways, on a wafer level, which may be coupled to a wafer of fully fabricated integrated circuits. Such conductor carriers include an insulating body having two major surfaces with conductors disposed on each of those surfaces, and conductors disposed within the insulating body so as to provide signal continuity between various conductors on each of the two surfaces. An assembly can be formed by permanently or removably attaching the conductor carrier to the wafer. Conductor carriers may include an evacuation pathway suitable for removing air, or other gases, from between the conductor and the wafer so as to create a pressure differential that urges the conductor carrier into contact with the wafer. Conductor carriers may include a groove which is suitable for receiving a sealing ring; and may include a street map which is suitable for providing guidance to a wafer sawing operation.

Abstract: Reduced impedance mismatches are obtained when coupling electrical signalling media by replacing conventional connector architectures, which disrupt transmission line characteristics, with an electrical coupling means that permits the electrical signalling media to present a planar interface for interconnection.

Abstract: Methods and apparatus are provided for I/O pads of unsingulated integrated circuits, to be connected to electrical equipment. A translator plate is interposed between a wafer and tester. The translator plate includes a substrate having two major opposing surfaces, each surface having terminals disposed thereon, and electrical pathways disposed through the substrate to provide for electrical continuity between at least one terminal on a first surface and at least one terminal on the second surface. The translator plate, when interposed between wafer and tester, makes electrical contact with one or more I/O pads of a plurality of integrated circuits on the wafer, providing an electrical pathway therethrough. An anisotropic conductor is disposed between the wafer and the translator plate. A vibratory mechanism, oriented to provide substantially horizontal vibratory motion to the wafer, may be coupled to the wafer to assist disposing the translator plate and anisotropic conductor over the wafer.

Abstract: Methods and apparatus are provided for I/O pads of unsingulated integrated circuits, to be connected to electrical equipment. A translator plate is interposed between a wafer and tester. The translator plate includes a substrate having two major opposing surfaces, each surface having terminals disposed thereon, and electrical pathways disposed through the substrate to provide for electrical continuity between at least one terminal on a first surface and at least one terminal on the second surface. The translator plate, when interposed between wafer and tester, makes electrical contact with one or more I/O pads of a plurality of integrated circuits on the wafer, providing an electrical pathway therethrough. An anisotropic conductor is disposed between the wafer and the translator plate. A vibratory mechanism, oriented to provide substantially horizontal vibratory motion to the wafer, may be coupled to the wafer to assist disposing the translator plate and anisotropic conductor over the wafer.

Abstract: Reduced impedance mismatches are obtained when coupling electrical signalling media by replacing conventional connector architectures, which disrupt transmission line characteristics, with an electrical coupling means that permits the electrical signalling media to present a planar interface for interconnection.

Abstract: Methods and apparatus are provided for I/O pads of unsingulated integrated circuits, to be connected to electrical equipment. A translator plate is interposed between a wafer and tester. The translator plate includes a substrate having two major opposing surfaces, each surface having terminals disposed thereon, and electrical pathways disposed through the substrate to provide for electrical continuity between at least one terminal on a first surface and at least one terminal on the second surface. The translator plate, when interposed between wafer and tester, makes electrical contact with one or more I/O pads of a plurality of integrated circuits on the wafer, providing an electrical pathway therethrough. An anisotropic conductor is disposed between the wafer and the translator plate. A vibratory mechanism, oriented to provide substantially horizontal vibratory motion to the wafer, may be coupled to the wafer to assist disposing the translator plate and anisotropic conductor over the wafer.

Abstract: A unified process of making an electrical structure includes performing a plurality of laser etching operations on workpiece, without removing the workpiece from a laser processing system. The workpiece includes a conductive material disposed on an electrically insulating substrate, and the plurality of laser etching operations include, but are not limited to, two or more of forming a fiducial, forming thick metal traces separated by high aspect ratio spaces, cutting an alignment hole, cutting a folding line, and singulating the electrical structure. In another aspect of the invention, a database is prepared, and communicatively coupled to the laser processing system to provide control signals that direct a portion of the plurality of operations of the laser processing system, wherein each plurality of etching operations is defined with respect to a common coordinate system.

Abstract: A multiple circuit board package employing solder balls and method and apparatus for fabricating same is described. Two or more printed circuit boards and a plurality of electronic devices are joined together using solder balls. Alternatively, three or more printed circuit boards are joined together using the solder balls. A novel and improved solder ball connection is disclosed, along with a fixture for aligning and fixing the disposition of the pads and the solder balls during a heating cycle in which the circuit boards are placed under pressure while the solder balls are re-flowed for making an electrical connection.

Abstract: A method of manufacturing electronic circuitry and the resulting hardware is described in which a conduction plate is formed achieving separate electrical conducting paths for application specific signals is engaged with an electronic circuit package containing a wide range of elements including one or more integrated circuits, chip packages, multichip modules printed circuit boards and cables. One or more of these elements are assembled into the circuit package where all or a major portion of the element conductors are routed to terminals positioned for electrical connection between the circuit apparatus and the electrical conduction plate. The conduction plate completes the electrical interconnection of the circuit package by providing the application specific conduction paths, using various techniques for creating electrical conduction, such as severing segments of a generalized conductive grid to establish desired conduction paths.