Abstract: An object of the present invention is to provide a DC-DC converter control circuit capable of maintaining, even when any one of a plural number of DC-DC converters enters the abnormal state due to the occurrence of a failure, a voltage relationship between the output voltage of the faulty DC-DC converter and the output voltage of another DC-DC converter. An error amplifier ERA1G has an inverting input, a first non-inverting input, and a second non-inverting input. A first divided voltage VV1 provided from a first voltage divider circuit VD1 is fed into the inverting input; a reference voltage e1G from ground is fed into the first non-inverting input; and a second divided voltage VV2 provided from a second voltage divider circuit VD2 is fed into the second non-inverting input. The error amplifier ERA1G amplifies the error between the lower of the two voltage inputs fed into the two non-inverting inputs (i.e.

Abstract: A DC-DC converter having conversion efficiency that is not lowered by input voltage change. A mode control circuit of the DC-DC converter monitors the input voltage, output voltage generated from the input voltage, and output current. The output current changes in accordance with the output voltage. Based on the input voltage, output voltage, and consumption current of a controller of the DC-DC converter, the mode control circuit generates a signal that is in accordance with load current in which efficiency of a switching regulator and efficiency of a linear regulator are substantially the same. The mode control circuit further compares a signal corresponding to the output current and the signal that is in accordance with the load current to generate a mode control signal. The controller operates the DC-DC converter as the switching regulator or the linear regulator in accordance with the mode control signal.

Abstract: A power supply circuit includes an output transistor including a source coupled to power supply voltage, and a drain from which output voltage is outputted; a first error amplifier powered by the power supply voltage and outputting a signal based on a potential difference between the output voltage and a reference voltage; a buffer transistor including a gate coupled to the output of the first error amplifier, and a source coupled via a constant current source to the power supply voltage and coupled to a gate of the output transistor; a current detection transistor coupled to the output transistor such that a gate and source are shared; and an overcurrent protection circuit configured to limit the drain current of the buffer transistor based on the increase of the drain current of the current detection transistor and thereby control the output current of the output transistor.

Abstract: A DC-DC converter control circuit can maintain a relationship of voltages established among the output voltages even when the output voltages of DC-DC converters are independently controlled. A first reference voltage with which a high-potential back-gate voltage is controlled and a second reference voltage with which a supply voltage is controlled are dynamically controlled to be varied independently from one another. A supply voltage is applied to the inverting input terminal of a second differential-input amplifier. The second reference voltage is applied to the first non-inverting input terminal of the second differential-input amplifier, and the first reference voltage is applied to the second non-inverting input terminal thereof. The second differential-input amplifier amplifies the difference between a lower one of the first and second reference voltages applied to the two non-inverting input terminals thereof and the supply voltage applied to the inverting input terminal thereof.

Abstract: According to one aspect of the embodiment, a linear regulator circuit includes an output transistor outputting an output current based on a input voltage, an error amplifier outputting a control signal based on an electric potential difference between an output voltage based on the output current and a reference voltage, a buffer circuit coupled between the error amplifier and the output transistor, and a drive capability adjustment circuit adjusting a load drive capability of the buffer circuit in synchronization with the output current.

Abstract: A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.

Abstract: A first power supply line and having a first conductivity type a second transistor coupled between the first transistor and a second power supply line, and having the first conductivity type an output unit driving a first control signal causing the first transistor to become conductive, based on a drive voltage, and outputting the first control signal to the first transistor and a boot strap circuit including a capacitor having a first end coupled to a node of the first transistor and the second transistor and supplying the output unit with the drive voltage based on the capacitor, wherein an electric potential of the first end is reduced before the first transistor becomes conductive.

Abstract: A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.

Abstract: According to an embodiment, a DC-DC converter comprises: an error amplifier that receives a soft start signal and amplifies a difference between an output voltage signal and a reference voltage signal; a PWM control circuit that controls ON and OFF states of a first switching transistor and a second switching transistor based on the output of the error amplifier; a frequency divider that divides a frequency signal and outputting a divided frequency signal; an accumulator that performs an adding operation based on the divided frequency signal and a control signal; and a DA converter that generates the soft start signal based on an output of the accumulator.

Abstract: According to one aspect of the invention, a DC-DC converter including a soft-start function of a soft start in response to a soft-start signal, comprises: a detection circuit that detects whether the soft-start signal is active at an end of a soft-start operation; and an output voltage control circuit that controls an output voltage based on detection result of the detection circuit.

Abstract: A DC-DC converter prevents localization of switching operations at light loads and is able to improve power conversion efficiency. The DC-DC converter of some variations performs pulse frequency modulation control at light loads, and includes a reducing circuit configured to skip an oscillation frequency signal at light loads and to generate a skipped signal.

Abstract: A differential output DC-DC converter capable of decreasing power consumption is presented. The differential output DC-DC converter 1 comprises output terminals VP and VM connected to both ends of load, and a switching regulator 10 for passing a source current. It further comprises a third transistor FET3, a choke coil L2, and a fourth transistor FET4 for rectifying a sink current in a flowing direction, and further a second regulator for allowing the sink current to flow, and issuing a voltage higher than a grounding point GND voltage and lower than a voltage of an output terminal VP, to an output terminal VM.

Abstract: A DC-DC conversion circuit is configured by including a plurality of control signal generation circuits, a plurality of soft-start control circuits, and a start control circuit. The plurality of control signal generation circuits correspond to the plurality of control signals, and generate a corresponding control signal of the plurality of control signals based on a corresponding output value of a plurality of output values. The plurality of soft-start control circuits correspond to the plurality of control signals, and control a variation of the corresponding control signal at a start time of the DC-DC conversion circuit. The start control circuit instructs the corresponding soft-start control circuit to start operation in accordance with a change of the control signal taking part in an output control at the start time of the DC-DC conversion circuit.

Abstract: In the following B cycles, the second frequency-divided signal fA is maintained at a low level, while the third frequency-divided signal fB is maintained at a high level. The three-modulus prescaler 13 has a frequency division value (M?1) if the pseudo random values are negative values, and a frequency division value (M+1) if the pseudo random values are positive values, in accordance with the signs of the pseudo random values outputted from the ?? modulator 8. After that, the frequency division value becomes M. A frequency division value of (MN+A+Bx) including the pseudo random value Bx is obtained in the comparison frequency divider 4. A fractional frequency division operation can be realized through ?? modulation by using the pseudo random numbers including negative values, as they are.

Abstract: A ?? modulator for producing a modulation signal for modulating a frequency division ratio of a comparison frequency divider of a PLL circuit. A plurality of integrators connected in series integrate an input signal and output overflow signals when the integrated value has exceeded a predetermined value. Differentiators transfer the overflow signals of the integrators. An adder multiplies predetermined coefficients by output signals output from the differentiators and adds the multiplied values. The absolute values of the predetermined coefficients of the adder are set to be less than the predetermined value. This setting decreases the modulation width of the modulation signal.

Abstract: A DC-DC converter reducing reverse current and maintaining high conversion efficiency under a light load. The DC-DC converter perform pulse width modulation (PWM) or pulse frequency modulation (PFM) and includes a drive control circuit generating a first drive signal and a second drive signal activating and inactivating a first transistor and a second transistor in a complementary manner. A reversed flow detection circuit detects current flowing to the second transistor and generates a detection signal controlling activation and inactivation of the second transistor. A detection signal invalidation circuit, coupled to the reversed flow detection circuit and the drive control circuit, receiving an operation switch signal and invalidating the detection signal in response to the operation switch signal during at least a certain period of the PWM.

Abstract: To provide a control circuit for a synchronous rectifier-type DC-DC converter, a synchronous rectifier-type DC-DC converter and a control method thereof in which, in a light load state and a no-load state, an output voltage can be dropped to thus prevent an overshoot state from continuing.

Abstract: To provide a control circuit of a current mode DC-DC converter, a current mode DC-DC converter and a control method thereof having excellent high-speed responsiveness with respect to fluctuations in output voltage. The control circuit of the current mode DC-DC converter serves as a DC-DC converter 1 that controls a peak value of a coil current and comprises a window comparator that detects whether an output voltage VOUT is within a predetermined voltage range including a target voltage, and a peak current setting unit that sets a peak current setting value of a coil current to a lower limit value or an upper limit value in response to a high or low voltage level of the output voltage VOUT, in the case that the output voltage VOUT is not within the predetermined voltage range including the target voltage.

Abstract: The control circuit comprises: a detecting portion COMP1 for detecting a status transition of a first signal FR at the connecting point P which changes at a constant cycle corresponding to current flowing through the antiparallel diode D when the main switch device FET is turned OFF; and a phase difference adjusting portion 30, 40 for adjusting the phase difference by adjusting the output timing of the second signal FP corresponding to a phase difference between the phase of the first signal FR detected by the detecting portion COMP1 and the phase of the second signal FP generated based on the first signal of one cycle before and the rectification switch device FET2 is turned ON corresponding to the second signal FP whose output timing is adjusted by the phase difference adjusting portion 30, 40.

Abstract: The control circuit 30 of power supply unit and power supply unit 10 controlling output power with electric power supplied from the external power 15, comprise a monitoring portion 40 monitoring current I1 and voltage outputted from the external power supply 15 and output power of the external power supply 15 and a setting portion e1 which sets an upper limit value of current outputted from the external power supply 15 based on a monitoring result of the monitoring portion 40.