Abstract: A DC-DC converter for preventing through current from causing erroneous operation of an ideal diode. A first transistor for receiving input voltage is connected to an ideal diode, which includes a second transistor and a comparator for detecting current flowing through the second transistor and generating a detection signal. A control circuit generates a switching signal for turning the first transistor on and off so as to keep the output voltage constant. A pulse generation circuit generates a pulse signal for turning off the second transistor before the first transistor is turned on and keeping the second transistor turned off for a predetermined period from when the first transistor is turned on. An erroneous operation prevention circuit generates a control signal for keeping the second transistor turned off from when the second transistor is turned off to when the first transistor is turned on.

Abstract: The invention provides a DC-DC converter capable of being started up in a state in which an input voltage is low and capable of being structured without increasing a circuit size. A back-gate voltage (Vsb) is outputted from a back-gate voltage generating circuit (VBGN), and is inputted to a back gate of a transistor (FET1). During a period during which an output voltage (Vout) is lower than a reference voltage (e0), an oscillation signal (OS1) is inputted to a gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at a grounded voltage. Therefore, the transistor (FET1) has a reference threshold voltage (Vto). On the other hand, during a period during which the output voltage (Vout) is higher than the reference voltage (e0), a pulse signal (PS) is inputted to the gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at an output voltage of a charge pump portion (5). Therefore, the transistor (FET1) has a threshold voltage higher than the reference threshold voltage (Vto).

Abstract: A DC-DC converter applicable to a wide input voltage range. An error amplifier compares a divided voltage, which is generated by dividing output voltage with a plurality of resistors, and a reference voltage to generate an error signal. A voltage source generates an offset signal by offsetting the error signal. A PWM comparator compares the offset signal with a triangular wave signal to generate a drive signal for controlling activation and inactivation of a first output transistor and a second transistor at a duty corresponding to the comparison result. An offset controller determines the ratio between the output voltage and the input voltage and controls the offset voltage of the voltage source in accordance with the determination.

Abstract: A sigma-delta modulator for generating a modulation signal that modulates a frequency division ratio of a comparator/frequency divider of a PLL circuit. Series-connected integrators accumulate an input signal and output overflow signals when their accumulated values exceed a predetermined value. Differentiators transfer the overflow signals of the integrators. An adder multiplies output signals output from the differentiators by a predetermined coefficient and adds the products. A control circuit for transferring the accumulated value in synchronization with a clock signal of each integrator is connected between the integrator of a final stage and the integrator of the preceding stage. The control circuit reduces the modulation width of the modulation signal without reducing the order number of the modulator.

Abstract: It is intended to provide a control circuit of power supply, a power supply and a control method thereof capable of achieving power saving in an integrated circuit and reducing a delay time of the integrated circuit. The control circuit 50 of a power supply 10 which outputs plural DC voltages VCC, VBGP, VBGN each having a different voltage value includes a voltage changing portion SW1 which detects an output current I1 relating to a first DC voltage VCC which is one of the plural DC voltages and sets at least one DC voltage except the first DC voltage VCC based on the detected output current I1, and the like.

Abstract: An object of the present invention is to provide a DC-DC converter control circuit capable of maintaining, even when any one of a plural number of DC-DC converters enters the abnormal state due to the occurrence of a failure, a voltage relationship between the output voltage of the faulty DC-DC converter and the output voltage of another DC-DC converter. An error amplifier ERA1G has an inverting input, a first non-inverting input, and a second non-inverting input. A first divided voltage VV1 provided from a first voltage divider circuit VD1 is fed into the inverting input; a reference voltage e1G from ground is fed into the first non-inverting input; and a second divided voltage VV2 provided from a second voltage divider circuit VD2 is fed into the second non-inverting input. The error amplifier ERA1G amplifies the error between the lower of the two voltage inputs fed into the two non-inverting inputs (i.e.

Abstract: Disclosed are a control circuit and control method for a comparator-controlled type DC-DC converter that can prevent the generation of audible noise due to the difference between relevant switching frequencies and prevent the increase in the input power source ripple voltage. A phase comparator FC outputs a compared-result signal CONT in correspondence with the phase difference between an output signal FP2 and a delay signal FR1. A delay circuit DLY2 performs a feedback control for adjusting the amount of retardation time in correspondence with the compared-result signal CONT. And, the delay circuit DLY2 outputs a delay signal FR2 after the passage of a prescribed amount of retardation time from the time when the falling edge of an output signal SQB2 has been input.

Abstract: An object of the present invention is to provide a DC-DC converter control circuit that, even when a plurality of output voltages of DC-DC converters is controlled independently of one another, can maintain a predetermined relationship of voltages established among the output voltages. A first reference voltage with which a high-potential back-gate voltage is controlled and a second reference voltage with which a supply voltage is controlled are dynamically controlled to be varied independently from one another. A supply voltage is applied to the inverting input terminal of a second differential-input amplifier. The second reference voltage is applied to the first non-inverting input terminal of the second differential-input amplifier, and the first reference voltage for a first DC-DC converter is applied to the second non-inverting input terminal thereof.

Abstract: A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.

Abstract: Disclosed are a control circuit and control method for a comparator-controlled type DC-DC converter that can prevent the generation of audible noise due to the difference between relevant switching frequencies and prevent the increase in the input power source ripple voltage. A phase comparator FC outputs a compared-result signal CONT in correspondence with the phase difference between an output signal FP2 and a delay signal FR1. A delay circuit DLY2 performs a feedback control for adjusting the amount of retardation time in correspondence with the compared-result signal CONT. And, the delay circuit DLY2 outputs a delay signal FR2 after the passage of a prescribed amount of retardation time from the time when the falling edge of an output signal SQB2 has been input.

Abstract: The invention provides a DC-DC converter capable of being started up in a state in which an input voltage is low and capable of being structured without increasing a circuit size. A back-gate voltage (Vsb) is outputted from a back-gate voltage generating circuit (VBGN), and is inputted to a back gate of a transistor (FET1). During a period during which an output voltage (Vout) is lower than a reference voltage (e0), an oscillation signal (OS1) is inputted to a gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at a grounded voltage. Therefore, the transistor (FET1) has a reference threshold voltage (Vto). On the other hand, during a period during which the output voltage (Vout) is higher than the reference voltage (e0), a pulse signal (PS) is inputted to the gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at an output voltage of a charge pump portion (5). Therefore, the transistor (FET1) has a threshold voltage higher than the reference threshold voltage (Vto).

Abstract: A control circuit for a DC-DC converter that prevents erroneous operations during high ON-duty operation. In response to an H-level pulse signal, a random delay circuit generates a delayed pulse signal that rises to an H level within one cycle of the pulse signal. The random delay circuit randomly changes the delay time of the delayed pulse signal. Even if noise causes the timing at which a current comparison signal rises to an H level to be delayed to later than the timing at which an H-level pulse signal is provided to the set terminal of an FF circuit, the FF circuit receives at its reset terminal an H-level delayed pulse signal that is provided prior to the H-level pulse signal. The FF circuit then inactivates the output transistor.

Abstract: A DC-DC converter applicable to a wide input voltage range. An error amplifier compares a divided voltage, which is generated by dividing output voltage with a plurality of resistors, and a reference voltage to generate an error signal. A voltage source generates an offset signal by offsetting the error signal. A PWM comparator compares the offset signal with a triangular wave signal to generate a drive signal for controlling activation and inactivation of a first output transistor and a second transistor at a duty corresponding to the comparison result. An offset controller determines the ratio between the output voltage and the input voltage and controls the offset voltage of the voltage source in accordance with the determination.

Abstract: It is an object of the present invention to provide a control circuit and a control method for a current mode control type DC—DC converter capable of preventing a subharmonic oscillation even if an on-duty is not less than 50% and capable of preventing a switching frequency from fluctuating depending on an input voltage. When a high-level output signal Vo1 is inputted to a reset input terminal R of a flip-flop FF, a transistor FET1 is turned off. A phase comparator FC outputs a comparison result signal CONT in accordance with a phase difference between a delay signal FP and a reference signal FR. A delay circuit DLY outputs a high-level delay signal FP after the passage of a delay time DT adjusted in accordance with the comparison result signal CONT from the turn-off of the transistor FET1. The transistor FET1 is turned on in accordance with an input of the high-level delay signal FP.

Abstract: A DC-DC converter having conversion efficiency that is not lowered by input voltage change. A mode control circuit of the DC-DC converter monitors the input voltage, output voltage generated from the input voltage, and output current. The output current changes in accordance with the output voltage. Based on the input voltage, output voltage, and consumption current of a controller of the DC-DC converter, the mode control circuit generates a signal that is in accordance with load current in which efficiency of a switching regulator and efficiency of a linear regulator are substantially the same. The mode control circuit further compares a signal corresponding to the output current and the signal that is in accordance with the load current to generate a mode control signal. The controller operates the DC-DC converter as the switching regulator or the linear regulator in accordance with the mode control signal.

Abstract: A differential output DC-DC converter capable of decreasing power consumption is presented. The differential output DC-DC converter 1 comprises output terminals VP and VM connected to both ends of load, and a switching regulator 10 for passing a source current. It further comprises a third transistor FET3, a choke coil L2, and a fourth transistor FET4 for rectifying a sink current in a flowing direction, and further a second regulator for allowing the sink current to flow, and issuing a voltage higher than a grounding point GND voltage and lower than a voltage of an output terminal VP, to an output terminal VM.

Abstract: A self-excited multi-phase DC—DC converter having satisfactory responsiveness when its load suddenly changes. A control unit of the converter compares output currents of first and second converter units. Based on the comparison result, the control unit generates control signals to operate a converter unit through which a smaller output current flows. For example, when an output voltage of the converter decreases due to a sudden change in the load while the first converter unit is operating to supply current, the second converter unit through which a smaller output current flows is operated to increase the output voltage.

Abstract: A control circuit for a DC-DC converter that prevents erroneous operations during high ON-duty operation. In response to an H-level pulse signal, a random delay circuit generates a delayed pulse signal that rises to an H level within one cycle of the pulse signal. The random delay circuit randomly changes the delay time of the delayed pulse signal. Even if noise causes the timing at which a current comparison signal rises to an H level to be delayed to later than the timing at which an H-level pulse signal is provided to the set terminal of an FF circuit, the FF circuit receives at its reset terminal an H-level delayed pulse signal that is provided prior to the H-level pulse signal. The FF circuit then inactivates the output transistor.

Abstract: A self-excited multi-phase DC-DC converter having satisfactory responsiveness when its load suddenly changes. A control unit of the converter compares output currents of first and second converter units. Based on the comparison result, the control unit generates control signals to operate a converter unit through which a smaller output current flows. For example, when an output voltage of the converter decreases due to a sudden change in the load while the first converter unit is operating to supply current, the second converter unit through which a smaller output current flows is operated to increase the output voltage.

Abstract: A sigma-delta modulator for generating a modulation signal that modulates a frequency division ratio of a comparator/frequency divider of a PLL circuit. Series-connected integrators accumulate an input signal and output overflow signals when their accumulated values exceed a predetermined value. Differentiators transfer the overflow signals of the integrators. An adder multiplies output signals output from the differentiators by a predetermined coefficient and adds the products. A control circuit for transferring the accumulated value in synchronization with a clock signal of each integrator is connected between the integrator of a final stage and the integrator of the preceding stage. The control circuit reduces the modulation width of the modulation signal without reducing the order number of the modulator.