Abstract: A ?? modulator for producing a modulation signal for modulating a frequency division ratio of a comparison frequency divider of a PLL circuit. A plurality of integrators connected in series integrate an input signal and output overflow signals when the integrated value has exceeded a predetermined value. Differentiators transfer the overflow signals of the integrators. An adder multiplies predetermined coefficients by output signals output from the differentiators and adds the multiplied values. The absolute values of the predetermined coefficients of the adder are set to be less than the predetermined value. This setting decreases the modulation width of the modulation signal.

Abstract: A fractional-N-PLL frequency synthesizer that reduces the spurious caused by a phase error is provided. A reference phase error is determined from a plurality of phase errors generated between a reference signal and a comparison signal when the fractional-N-PLL frequency synthesizer is locked. Then, any phase error equal to or smaller than the reference phase error is canceled.

Abstract: A toggle flip-flop circuit that increases operational speed and decreases power consumption with a simplified configuration. The toggle flip-flop circuit has a master latch circuit, which includes an emitter-coupled logic (ECL) circuit, and a slave latch circuit, which includes an ECL circuit. The master slave circuit and the slave latch circuit are driven by the same ECL drive circuit.

Abstract: A fractional-N-PLL frequency synthesizer that reduces the spurious caused by a phase error is provided. A reference phase error is determined from a plurality of phase errors generated between a reference signal and a comparison signal when the fractional-N-PLL frequency synthesizer is locked. Then, any phase error equal to or smaller than the reference phase error is canceled.

Abstract: A prescaler which can be used in a PLL includes a counter section and an extender section. The counter section has a pair of staged, synchronous flip-flops which generate a frequency divided signal by frequency dividing an input oscillation signal by either two or three. The extender section has a plurality of staged, asynchronous flip-flops which generates a second frequency divided signal. A switching circuit connected between the extender section and the counter section controls whether the counter section operates as either a binary counter or a ternary counter. Power conservation is achieved by limiting the counter section to only a pair of flip-flops.

Abstract: A PLL including a phase comparator, a VCO, and a charge pump further includes a reset circuit. The reset circuit detects whether both of the charge pump transistors are in an ON state, and if so, generates a reset signal which inhibits the UP and DOWN signals generated by the phase comparator. The reset circuit includes first and second detection circuits and a signal generating circuit.