Patents by Inventor Morio Iwamizu

Morio Iwamizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140375244
    Abstract: In a stepping motor drive device, it is possible to prevent malfunction due to negative current from a stepping motor of a plurality of power MOSFETs that apply drive voltage in a complementary way to paired coils of the stepping motor. A fall delay circuit delays the timing of the fall of input pulse signals applied in a complementary way to the gate of each of a plurality of MOSFETs that apply drive voltage in a complementary way to paired coils of a stepping motor by a time Td, wherein Td>Trise?Tfall, in accordance with a rise time Trise when turning on, and a fall time Tfall when turning off, the relevant MOSFET, and after one MOSFET is turned on, another MOSFET is turned off.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 25, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Morio IWAMIZU
  • Patent number: 8890581
    Abstract: A driving circuit for driving an insulated gate semiconductor device based on a voltage of an externally-inputted gate signal, where the insulated gate semiconductor device has a source, a drain and a gate, and a parasitic capacitor exists between the drain and the gate. The driving circuit includes a gate voltage controlling semiconductor device disposed between, and connecting, the gate and the source of the insulated gate semiconductor device. The gate voltage controlling semiconductor device has a source and a gate, and is driven by a current charging the parasitic capacitor. The driving circuit also includes a pull-up device disposed between, and connecting, the source and the drain of the gate voltage controlling semiconductor device.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: November 18, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Morio Iwamizu
  • Publication number: 20120038392
    Abstract: A driving circuit for driving an insulated gate semiconductor device based on a voltage of an externally-inputted gate signal, where the insulated gate semiconductor device has a source, a drain and a gate, and a parasitic capacitor exists between the drain and the gate. The driving circuit includes a gate voltage controlling semiconductor device disposed between, and connecting, the gate and the source of the insulated gate semiconductor device. The gate voltage controlling semiconductor device has a source and a gate, and is driven by a current charging the parasitic capacitor. The driving circuit also includes a pull-up device disposed between, and connecting, the source and the drain of the gate voltage controlling semiconductor device.
    Type: Application
    Filed: July 28, 2011
    Publication date: February 16, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Morio IWAMIZU
  • Patent number: 8033721
    Abstract: A temperature sensor circuit is provided that facilitates preventing a too-high overshooting voltage from occurring at an output terminal when a power supply is connected to the temperature sensor circuit. The temperature sensor circuit includes a short-circuiting device, disposed in parallel to depletion mode NMOS, that short-circuits the drain and source of depletion mode NMOS when a power supply is connected; and delay device that transmits a signal for short-circuiting the drain and source of depletion mode NMOS for a certain period from the time point of power supply connection to short-circuiting device for preventing the voltage at output terminal of temperature sensor circuit from overshooting.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: October 11, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takatoshi Ooe, Ryuu Saitou, Morio Iwamizu
  • Patent number: 7777518
    Abstract: A buffer circuit is provided between a gate terminal of a pull-down transistor and a threshold circuit receiving a gate signal as an input signal. A voltage applied to an output terminal of a power semiconductor element from an external battery power supply is supplied to the buffer circuit through a resistive element. The buffer circuit converts the level of an on-signal output from the threshold circuit into a voltage higher than the threshold of the pull-down transistor, so that the pull-down transistor operates surely to turn off the power semiconductor element even when the level of the gate signal is low. Thus, there is provided a semiconductor integrated circuit device having a power semiconductor element which can be turned off by sure operation of a pull-down semiconductor element.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: August 17, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Yoshiaki Toyoda, Kenichi Ishii, Morio Iwamizu
  • Publication number: 20090289670
    Abstract: A buffer circuit is provided between a gate terminal of a pull-down transistor and a threshold circuit receiving a gate signal as an input signal. A voltage applied to an output terminal of a power semiconductor element from an external battery power supply is supplied to the buffer circuit through a resistive element. The buffer circuit converts the level of an on-signal output from the threshold circuit into a voltage higher than the threshold of the pull-down transistor, so that the pull-down transistor operates surely to turn off the power semiconductor element even when the level of the gate signal is low. Thus, there is provided a semiconductor integrated circuit device having a power semiconductor element which can be turned off by sure operation of a pull-down semiconductor element.
    Type: Application
    Filed: May 26, 2009
    Publication date: November 26, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Yoshiaki TOYODA, Kenichi ISHII, Morio IWAMIZU
  • Publication number: 20090153227
    Abstract: A temperature sensor circuit is provided that facilitates preventing a too-high overshooting voltage from occurring at an output terminal when a power supply is connected to the temperature sensor circuit. The temperature sensor circuit includes a short-circuiting device, disposed in parallel to depletion mode NMOS, that short-circuits the drain and source of depletion mode NMOS when a power supply is connected; and delay device that transmits a signal for short-circuiting the drain and source of depletion mode NMOS for a certain period from the time point of power supply connection to short-circuiting device for preventing the voltage at output terminal of temperature sensor circuit from overshooting.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 18, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Takatoshi OOE, Ryuu SAITOU, Morio IWAMIZU