Abstract: A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

Abstract: A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

Abstract: A liquid crystal display device having an alignment layer stopper which is formed external to a display area to suppress the generation of an electric field between signal lines and the alignment layer stopper, wherein the alignment layer stopper includes a second conductive layer SP formed above the first substrate when the alignment layer stopper is formed by coating and a first conductive layer SH formed below the second conductive layer SP through an insulating film and arranged in such a manner that its marginal parts in the longitudinal direction of the second conductive layer SP are exposed when viewed from the plane direction from the second conductive layer SP, and the first conductive layer SH is formed in a thin film layer between signal lines arranged in the side parts of the display area and the second conductive layer SP.

Abstract: A liquid crystal display device having an alignment layer stopper which is formed external to a display area to suppress the generation of an electric field between signal lines and the alignment layer stopper, wherein the alignment layer stopper includes a second conductive layer SP formed above the first substrate when the alignment layer stopper is formed by coating and a first conductive layer SH formed below the second conductive layer SP through an insulating film and arranged in such a manner that its marginal parts in the longitudinal direction of the second conductive layer SP are exposed when viewed from the plane direction from the second conductive layer SP, and the first conductive layer SH is formed in a thin film layer between signal lines arranged in the side parts of the display area and the second conductive layer SP.

Abstract: A gate signal line drive circuit whose power consumption is reduced, is provided. In the gate signal line drive circuit having plural basic circuits outputting respective gate signals, each basic circuit includes a high voltage application switching element to which a first basic clock signal having high voltage in a signal high period is input, a low voltage application switching element that turns on at timing starting a signal low period, and outputs a low voltage, and a first low voltage application on control element having an input terminal to which a second basic clock signal subsequent to the first basic clock signal is input, and which turns on according to the signal high period, and outputs the voltage of the second basic clock signal to the control terminal of the low voltage application switching element.

Abstract: A display device with a touch panel includes: a plurality of scanning signal lines, which are aligned in a rectangular display region and in parallel with a side of the rectangular display region, to which an active potential as a potential for making a pixel transistor conductive is applied; drive pulse output circuits which sequentially apply the active potential to the scanning signal lines in the display region; a clock signal output circuit which applies a first clock signal as a clock signal for the drive pulse output circuits to a first clock signal line and stops the application of the first clock signal to the first clock signal line for a stop period during which the sequential application of the active potential is stopped in the middle thereof; and a touch panel control unit which detects contact with a display surface during the stop period.

Abstract: In a driving circuit, one output circuit has a scanning signal line, a first transistor which controls electrical connection between the scanning signal line and a clock signal line which has a gate connected to a first node, the first node which is at an active potential in a first time period including a time period during which the active potential is output to the scanning signal line, a second transistor which electrically connects the first node and an inactive signal line which has a potential to open the transistor in a second time period other than the first time period, and the second transistor has a gate connected to a second node, wherein the second node has two kinds of timings to be charged for retaining the active potential.

Abstract: There is provided a display device that suppresses an electrostatic discharge failure in a manufacturing stage, and improves a yield. A substrate provided in the display device includes: a display unit in which a plurality of pixel circuits, and a common electrode are formed; N (integer satisfying N?3) gate signal lines extending in the display unit; a gate driver circuit in which N shift register circuits connected to the respective gate signal lines to supply a gate signal are arranged outside of the display unit side by side; a common voltage main line arranged further outside of the gate driver circuit with respect to the display unit; and M common voltage sub-lines extending in M (1?M<N?1) spacings among (N?1) spacings between the respective N shift register circuits which are arranged side by side, from the common voltage main lines to the common electrode.

Abstract: A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.

Abstract: Provided is a gate signal line drive circuit including a shift register basic circuit for applying a high voltage for a signal high period and a low voltage for a signal low period to a gate signal line at the time of a screen display. The shift register basic circuit includes a gate line high voltage applying circuit applying a high voltage for the signal high period to the gate signal line, and a gate line low voltage applying circuit applying a low voltage to the gate signal line, wherein in the shift register basic circuit, the off-voltage is applied to the switch of the gate line low voltage applying circuit for a predetermined period at the time of a screen non-display.

Abstract: A gate signal line drive circuit and a display using the circuit, which suppress a leak current to reduce a power consumption. A gate signal line drive circuit that supplies a high voltage in a signal high period, and supplies a low voltage in a signal low period, the gate signal line drive circuit including: a high voltage supply switching element that turns on in response to the high period, supplies a voltage of a first basic clock signal to gate signal lines; a high voltage supply off control circuit that supplies a first low voltage to a switch of the high voltage supply switching element in response to the signal low period; and a low voltage supply switching circuit that supplies a second low voltage higher than the first low voltage to the gate signal lines in response to the signal low period.

Abstract: A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

Abstract: A circuit block of a driving circuit of a display device includes a first transistor that has a gate being connected to a first node having an active potential during an output period, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period, and controls electrical conduction between the first node and an inactive potential line, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line applied with a first period signal having an active potential at the time of termination of the output period.

Abstract: In a driving circuit, one output circuit has a scanning signal line, a first transistor which controls electrical connection between the scanning signal line and a clock signal line which has a gate connected to a first node, the first node which is at an active potential in a first time period including a time period during which the active potential is output to the scanning signal line, a second transistor which electrically connects the first node and an inactive signal line which has a potential to open the transistor in a second time period other than the first time period, and the second transistor has a gate connected to a second node, wherein the second node has two kinds of timings to be charged for retaining the active potential.

Abstract: Provided is a gate signal line drive circuit including a shift register basic circuit for applying a high voltage for a signal high period and a low voltage for a signal low period to a gate signal line at the time of a screen display. The shift register basic circuit includes a gate line high voltage applying circuit applying a high voltage for the signal high period to the gate signal line, and a gate line low voltage applying circuit applying a low voltage to the gate signal line, wherein in the shift register basic circuit, the off-voltage is applied to the switch of the gate line low voltage applying circuit for a predetermined period at the time of a screen non-display.

Abstract: A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.