Patents by Inventor Motoji Shiota
Motoji Shiota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220181581Abstract: A display device is provided with a first adhesive layer formed on a sealing layer in a display region and a flexible sheet formed on a resin layer on an opposite side of a TFT layer, in which a first inorganic insulating layer has a first slit, the flexible sheet has a second slit, and the first adhesive layer is formed in a state of extending from the display region to a frame region, and overlapping with the first slit and the second slit.Type: ApplicationFiled: March 11, 2019Publication date: June 9, 2022Inventors: Hiroki KAWAMURA, KEIJI AOTA, MOTOJI SHIOTA
-
Publication number: 20210005701Abstract: A display device includes a resin layer, a film substrate bonded to one surface of the resin layer by using an adhesive layer, a display region provided on another surface of the resin layer opposite to the one surface of the resin layer, and a frame region provided around the display region. In the film substrate, a first slit formed by removing thickness of a film substrate is formed. In the film substrate, the first slit is formed in at least a part of a region overlapping a region between a plurality of input terminals of a driving chip and a plurality of output terminals of the driving chip.Type: ApplicationFiled: March 2, 2018Publication date: January 7, 2021Inventors: TAKASHI MATSUI, MOTOJI SHIOTA, TAKESHI HORIGUCHI
-
Patent number: 10818626Abstract: Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.Type: GrantFiled: November 24, 2017Date of Patent: October 27, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Seiji Muraoka, Yukio Shimizu, Motoji Shiota
-
Patent number: 10811488Abstract: A display device includes a TFT layer provided in a display area, a bending section and a terminal in a non-active area, and a terminal wiring line that connects to the terminal through the bending section, and the terminal wiring line includes a first wiring line and a second wiring line each positioned on both sides of the bending section and a third wiring line that passes through the bending section and is electrically connected with each of the first wiring line and the second wiring line and curved so as to have recesses and protrusions.Type: GrantFiled: September 22, 2017Date of Patent: October 20, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Takashi Matsui, Yukio Shimizu, Gen Nagaoka, Motoji Shiota
-
Publication number: 20190364671Abstract: A mounting method includes a generating pressing force that presses a non-active region against a backup stage, and a compression bonding an electronic circuit board to terminals, after the non-active region is pressed against the backup stage by the pressing force generated in the generating a pressing step.Type: ApplicationFiled: March 29, 2017Publication date: November 28, 2019Inventors: Takushi MIHOTANI, Motoji SHIOTA
-
Publication number: 20190363153Abstract: A display device includes a TFT layer provided in a display area, a bending section and a terminal in a non-active area, and a terminal wiring line that connects to the terminal through the bending section, and the terminal wiring line includes a first wiring line and a second wiring line each positioned on both sides of the bending section and a third wiring line that passes through the bending section and is electrically connected with each of the first wiring line and the second wiring line and curved so as to have recesses and protrusions.Type: ApplicationFiled: September 22, 2017Publication date: November 28, 2019Inventors: Takashi MATSUI, Yukio SHIMIZU, Gen NAGAOKA, Motoji SHIOTA
-
Publication number: 20190295974Abstract: Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.Type: ApplicationFiled: November 24, 2017Publication date: September 26, 2019Applicant: SHARP KABUSHIKI KAISHAInventors: SEIJI MURAOKA, YUKIO SHIMIZU, MOTOJI SHIOTA
-
Patent number: 10224305Abstract: In order to inhibit defective connection between a bump of a semiconductor chip and an electrode pad of a substrate, a semiconductor device includes a substrate provided on a surface with a plurality of electrode pads 15, a semiconductor chip 20 provided on a surface with a plurality of bumps 21 substantially equal in size, and an anisotropic conductive film 30 interposed between the plurality of bumps 21 and the plurality of electrode pads 15 and electrically connecting each of the bumps 21 and corresponding one of the electrode pads 15. The plurality of electrode pads 15 includes a plurality of first electrode pads 15A positioned closest to an end 25 of the semiconductor chip 20, and a plurality of second electrode pads 15B positioned inside the plurality of first electrode pads 15A on the semiconductor chip 20. Each of the second electrode pads 15B is larger in area than each of the first electrode pads 15A.Type: GrantFiled: May 18, 2016Date of Patent: March 5, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Masaki Nakayama, Motoji Shiota, Takashi Matsui, Yasuhiko Tanaka, Hiroki Miyazaki, Seiji Muraoka
-
Publication number: 20190033646Abstract: A terminal connection structure includes a large panel-side terminal (a high resistance terminal) 28 having relatively high electric resistance, and a large flexible board-side terminal (a low resistance terminal) 30 having relatively low electric resistance and connected to the large panel-side terminal 28. The large flexible board-side terminal 30 includes separated large flexible board-side terminals (separated low resistance terminals) 30a that are arranged at intervals and have a width relatively larger in a distal end side portion 30a2 with respect to a basal end side portion 30a1.Type: ApplicationFiled: January 20, 2017Publication date: January 31, 2019Applicant: Sharp Kabushiki KaishaInventors: Yukio SHIMIZU, Motoji SHIOTA, Keiji AOTA
-
Patent number: 9995977Abstract: An array circuit board 11B includes a glass substrate, an IC chip 20, two ACFs 30, and a resin film 32. The IC chip 20 is disposed on the glass substrate. The ACFs 30 are disposed between the glass substrate and the IC chip 20 for electrically connecting the glass substrate and the IC chip 20 together. The ACFs 30 are separated from each other. The resin film 32 is made of resin material having cure shrinkage smaller than the ACFs 30 and disposed to fill a gap between the ACFs 30 adjacent to each other between the glass substrate and the IC chip 20.Type: GrantFiled: June 19, 2015Date of Patent: June 12, 2018Assignee: SHARP KABUSHIKI KAISHAInventors: Masaki Nakayama, Motoji Shiota, Takashi Matsui, Yasuhiko Tanaka, Hiroki Miyazaki
-
Publication number: 20180158795Abstract: In order to inhibit defective connection between a bump of a semiconductor chip and an electrode pad of a substrate, a semiconductor device includes a substrate provided on a surface with a plurality of electrode pads 15, a semiconductor chip 20 provided on a surface with a plurality of bumps 21 substantially equal in size, and an anisotropic conductive film 30 interposed between the plurality of bumps 21 and the plurality of electrode pads 15 and electrically connecting each of the bumps 21 and corresponding one of the electrode pads 15. The plurality of electrode pads 15 includes a plurality of first electrode pads 15A positioned closest to an end 25 of the semiconductor chip 20, and a plurality of second electrode pads 15B positioned inside the plurality of first electrode pads 15A on the semiconductor chip 20. Each of the second electrode pads 15B is larger in area than each of the first electrode pads 15A.Type: ApplicationFiled: May 18, 2016Publication date: June 7, 2018Inventors: MASAKI NAKAYAMA, MOTOJI SHIOTA, TAKASHI MATSUI, YASUHIKO TANAKA, HIROKI MIYAZAKI, SEIJI MURAOKA
-
Patent number: 9320150Abstract: A display apparatus is provided with: a frame; a display panel, which is fixed to the frame; and a plurality of flexible printed circuit boards, which are disposed adjacent to each other, and each of which has one end side pressure bonded to the display panel, and the other end side bent to the frame side, which is the reverse side of the display panel. The display apparatus has adhesive areas wherein a surface of the display panel is adhered and fixed to the frame, the adhesive areas being in areas overlapping the flexible printed circuit boards. In regions among the flexible printed circuit boards adjacent to each other, non-adhesive areas where the surface of the display panel is not adhered and fixed to the frame are provided.Type: GrantFiled: January 31, 2013Date of Patent: April 19, 2016Assignee: SHARP KABUSHIKI KAISHAInventors: Masaki Nakayama, Motoji Shiota, Takashi Matsui, Hiroki Miyazaki
-
Patent number: 9318454Abstract: This drive chip has a configuration that is provided with: a base main body; two terminal groups that are respectively disposed along the base main body sides in the longitudinal direction of the base main body, said sides facing each other; a narrow-pitch section in one terminal group wherein terminals are disposed in a zigzag manner in two or more rows, said narrow-pitch section having a narrow terminal pitch in the longitudinal direction; a rough pitch section in the one terminal group, said rough pitch section having a terminal pitch in the longitudinal direction wider than that of the narrow pitch section; and a dummy bump that is disposed between the two terminal groups, said dummy bump being disposed parallel to the rough pitch section.Type: GrantFiled: October 7, 2013Date of Patent: April 19, 2016Assignee: Sharp Kabushiki KaishaInventors: Takashi Matsui, Takeshi Horiguchi, Motoji Shiota
-
Patent number: 9217888Abstract: A liquid crystal display device includes: a liquid crystal panel having a display area and non-display area; a flexible substrate in the non-display area and connected to a control circuit substrate; a plurality of drivers in the non-display area; a plurality of connection wiring lines in the non-display area for connecting the flexible substrate to the plurality of drivers; a first driver; a second driver that is arranged further away from the flexible substrate than the first driver; a non-overlapping connection wiring line that connects the second driver to the flexible substrate and that does not overlap the first driver; and an overlapping connection wiring line that connects the second driver to the flexible substrate and that has a least a portion thereof overlapping the first driver.Type: GrantFiled: April 19, 2013Date of Patent: December 22, 2015Assignee: SHARP KABUSHIKI KAISHAInventors: Yukio Shimizu, Seiji Muraoka, Motoji Shiota, Takeshi Horiguchi
-
Patent number: 9207477Abstract: A display module 1 of the present invention includes a first board 3, a second board 4, a base film 5, and a circuit member 2. The first board 3 and the second board 4 are bonded together to face with each other. The base film 5 is provided between the first board 3 and the second board 4 and extends outwardly from an end of the first board 3. The base film 5 has an insulating property and the extended portion is bent to an outer surface side of one of the first board 3 and the second board 4. The circuit member 2 is formed on the base film 5.Type: GrantFiled: April 23, 2012Date of Patent: December 8, 2015Assignee: SHARP KABUSHIKI KAISHAInventors: Hiroki Miyazaki, Motoji Shiota, Takatoshi Kira, Gen Nagaoka, Seiji Muraoka, Makoto Tamaki, Keiji Aota, Yukio Shimizu, Takashi Matsui, Hiroki Nakahama, Hiroki Makino, Minoru Horino
-
Publication number: 20150334839Abstract: The present invention involves forming wiring sections on a substrate capable of UV-ray transmission, and fixing a component to be electrically connected to the wiring sections onto the substrate using a UV-curable ACF. When doing so, fluidity in the UV-curable ACF is produced by applying pressure to the component, and UV rays are directly projected from the surface of the substrate even onto the UV-curable ACF areas shielded by the wiring sections. The UV-curable ACF is made to be fluid by applying pressure to the component after increasing fluidity of the UV-curable ACF by heating.Type: ApplicationFiled: December 6, 2013Publication date: November 19, 2015Inventors: Hiroki NAKAHAMA, Motoji SHIOTA, Takashi MATSUI, Hiroki MIYAZAKI, Masaki NAKAYAMA
-
Publication number: 20150319849Abstract: The present invention provides a component securing structure that forms a wiring unit on a TFT glass substrate that is capable of transmitting UV light. A component, such as a driver IC and/or an FPC, is electrically connected to the wiring unit and is secured to the TFT glass substrate by a UV-curable ACF. An opening for transmitting UV light is formed in a light shielding layer of the wiring unit. UV light irradiated from the back side of the TFT glass substrate passes through the opening and directly irradiates the UV-curable ACF.Type: ApplicationFiled: December 9, 2013Publication date: November 5, 2015Applicant: SHARP KABUSHIKI KAISHAInventors: Yukio SHIMIZU, Motoji SHIOTA, Hiroki MIYAZAKI, Hiroki NAKAHAMA, Seiji MURAOKA, Takeshi HORIGUCHI
-
Publication number: 20150279792Abstract: This drive chip has a configuration that is provided with: a base main body; two terminal groups that are respectively disposed along the base main body sides in the longitudinal direction of the base main body, said sides facing each other; a narrow-pitch section in one terminal group wherein terminals are disposed in a zigzag manner in two or more rows, said narrow-pitch section having a narrow terminal pitch in the longitudinal direction; a rough pitch section in the one terminal group, said rough pitch section having a terminal pitch in the longitudinal direction wider than that of the narrow pitch section; and a dummy bump that is disposed between the two terminal groups, said dummy bump being disposed parallel to the rough pitch section.Type: ApplicationFiled: October 7, 2013Publication date: October 1, 2015Inventors: Takashi Matsui, Takeshi Horiguchi, Motoji Shiota
-
Patent number: 9148957Abstract: A wiring substrate (11) includes: a substrate; and, formed upon the substrate, a plurality of wiring lines, a plurality of circuit elements, and a plurality of connecting terminals (51) connected via the plurality of wiring lines. Each of the plurality of connecting terminals (51) includes a pair of protrusion parts (50), forming a depression part (60) between the pair of protrusion parts (50), and a depression electrode (52) that is disposed in the depression part (60) and that at least partially covers each protrusion of the pair of protrusion parts (50).Type: GrantFiled: March 1, 2012Date of Patent: September 29, 2015Assignee: SHARP KABUSHIKI KAISHAInventors: Takashi Matsui, Motoji Shiota, Hiroki Nakahama
-
Publication number: 20150109550Abstract: A liquid crystal display device includes: a liquid crystal panel having a display area and non-display area; a flexible substrate (13) in the non-display area and connected to a control circuit substrate; a plurality of drivers (21) in the non-display area; a plurality of connection wiring lines (27) in the non-display area for connecting the flexible substrate to the plurality of drivers; a first driver (21A); a second driver (21B) that is arranged further away from the flexible substrate than the first driver; a non-overlapping connection wiring line (32) that connects the second driver to the flexible substrate and that does not overlap the first driver; and an overlapping connection wiring line (31) that connects the second driver to the flexible substrate and that has a least a portion thereof overlapping the first driver.Type: ApplicationFiled: April 19, 2013Publication date: April 23, 2015Applicant: Sharp Kabushiki KaishaInventors: Yukio Shimizu, Seiji Muraoka, Motoji Shiota, Takeshi Horiguchi