Abstract: A liquid crystal display device includes: a liquid crystal panel having a display area and non-display area; a flexible substrate (13) in the non-display area and connected to a control circuit substrate; a plurality of drivers (21) in the non-display area; a plurality of connection wiring lines (27) in the non-display area for connecting the flexible substrate to the plurality of drivers; a first driver (21A); a second driver (21B) that is arranged further away from the flexible substrate than the first driver; a non-overlapping connection wiring line (32) that connects the second driver to the flexible substrate and that does not overlap the first driver; and an overlapping connection wiring line (31) that connects the second driver to the flexible substrate and that has a least a portion thereof overlapping the first driver.

Abstract: A display apparatus is provided with: a frame; a display panel, which is fixed to the frame; and a plurality of flexible printed circuit boards, which are disposed adjacent to each other, and each of which has one end side pressure bonded to the display panel, and the other end side bent to the frame side, which is the reverse side of the display panel. The display apparatus has adhesive areas wherein a surface of the display panel is adhered and fixed to the frame, the adhesive areas being in areas overlapping the flexible printed circuit boards. In regions among the flexible printed circuit boards adjacent to each other, non-adhesive areas where the surface of the display panel is not adhered and fixed to the frame are provided.

Abstract: A display module 1 of the present invention includes a first board 3, a second board 4, a base film 5, and a circuit member 2. The first board 3 and the second board 4 are bonded together to face with each other. The base film 5 is provided between the first board 3 and the second board 4 and extends outwardly from an end of the first board 3. The base film 5 has an insulating property and the extended portion is bent to an outer surface side of one of the first board 3 and the second board 4. The circuit member 2 is formed on the base film 5.

Abstract: A wiring substrate (11) includes: a substrate; and, formed upon the substrate, a plurality of wiring lines, a plurality of circuit elements, and a plurality of connecting terminals (51) connected via the plurality of wiring lines. Each of the plurality of connecting terminals (51) includes a pair of protrusion parts (50), forming a depression part (60) between the pair of protrusion parts (50), and a depression electrode (52) that is disposed in the depression part (60) and that at least partially covers each protrusion of the pair of protrusion parts (50).

Abstract: A liquid crystal display device (100) includes a glass substrate (110) having an LSI chip (130) and an FPC board (140) mounted thereon. A component ACF (150a) made of a single sheet is used to further mount discrete electronic components such as stabilizing capacitors (150) on the glass substrate (110). The component ACF (150a) has a size that covers not only a region where the discrete electronic components are to be mounted, but also the top surfaces of the LSI chip (130) and the FPC board (140) which are mounted first. By thus using the large component ACF (150a), a positional constraint upon adhering the component ACF (150a) to the glass substrate (110) is eliminated, reducing the area of a region where the discrete electronic components are mounted. By this, a board module miniaturized by reducing the area of a region where discrete electronic components are mounted is provided.

Abstract: A drive IC chip (21) including a circuit for driving a display region (41) is mounted on a panel substrate (11). An anisotropic conductive film (31) is interposed between the panel substrate (11) and the drive IC chip (21) and electrically connects the bump electrodes (22) of the drive IC chip (21) and the electrode pads (27) of the panel substrate (11). The anisotropic conductive film (31) is arranged to extend beyond all side surfaces (21b to 21d) other than one specific side surface (21a) of the drive IC chip (21).

Abstract: A wiring board of the present invention (1) is arranged so that: pads (30) arranged in a plurality of rows include: first-row pads (30a) connected to first metal wires (10a) among metal wires (10); and second-row pads (30b) connected to second metal wires (10b) among the metal wires (10), the first metal wires (10a) being longer than the second metal wires (10b); each of the first metal wires (10a) is formed so as to be separated from a corresponding one of the second-row pads (30b) by at least an insulating layer, and so as to have a widthwise center in a lower region below the corresponding second-row pad (30b); and each of the first metal wires (10a) has widthwise edges provided, in a plan view, beyond widthwise edges of a corresponding one of the second-row pads (30b) in a region in which the first metal wire (10a) overlaps with the corresponding second-row pad (30b).

Abstract: A wiring board of the present invention has pads disposed in a plurality of rows including: first row pads each being connected to a respective one of the connection wires that is long in length; and second row pads (30b) each being connected to a respective one of the connection wires that is shorter in length than that of first connection wires (10a) connected to the first row pads, each of the first connection wires (10a) being provided not in a region between adjacent ones of the second row pads (30b) but in a lower layer region of the second row pads (30b), in such a manner that at least a first insulating layer (20a) is sandwiched between the second row pads (30b) and the first connection wires (10a), and 0.8?W1/W2?1, where W1 is a line width of the first connection wires (10a) in the lower layer region of the second row pads (30b), and W2 is a width of the second row pads (30b).

Abstract: Provided is a semiconductor element in which decrease in reliability of wiring is suppressed. A driver IC (10) has a plurality of output bumps (12) arranged in the direction (direction A) along the long sides (11a and 11b). The output bumps include a plurality of source bumps (12a) arranged near the center section of the long side, and a plurality of gate bumps (12b) arranged towards the end portions of the long side. The source bumps are arranged close to the long side (11a), and the gate bumps are arranged closer to the long side (11b) than the source bumps.

Abstract: Disclosed is a device substrate wherein an insulating layer (60) having a terminal (24) formed on the surface thereof is formed over the entire surface of a glass substrate (20), excluding a display section, and therefore, the border (outer periphery) of the insulating layer (60) does not approach a region where an NCF (81) is provided, i.e., an area close to an LSI chip (40). This prevents the insulating layer (60) from being peeled off from the border thereof by the NCF (81), and thereby prevents the terminal (24) from breaking. Furthermore, the terminal (24) and a bump electrode (40a) are permanently pressure-bonded to each other by the elasticity of the insulating layer (60), and a stable electrical connection therebetween can be ensured.

Abstract: A region for mounting components such as an IC chip is sufficiently ensured on a glass substrate with which a liquid crystal panel is configured, without reducing the number of panel pieces to be taken from a large panel. A liquid crystal panel is composed of a first glass substrate (10) and a second glass substrate (20) which face each other with a liquid crystal therebetween. The first glass substrate (10) and the second glass substrate (20) are formed in substantially the same size in plan view and bonded together in a state in which these substrates are shifted from each other by a predetermined distance in the direction of the longer side or in the direction of the shorter side. Regions to become a frame (frame regions) are provided on both the first glass substrate (10) and the second glass substrate (20), and pads (60) are provided on both of these frame regions.

Abstract: Provided is a semiconductor chip having a narrowed pitch between terminals, the chip being capable of suppressing occurrence of poor connection between the chip and a substrate on which the chip is mounted. In an LSI chip including an input bump group, which is composed of a plurality of input bumps aligned in a line along one long side of its bottom surface, and an output bump group, which is composed of a plurality of output bumps arranged in a staggered manner along the other long side of the bottom surface, a dummy bump group is provided in an area between an area where the input bump group is provided and an area where the output bump group is provided, the dummy bump group including a plurality of rectangular dummy bumps which have long side extending along a direction perpendicular to the long sides of the bottom surface.

Abstract: A wiring board of the present invention (1) is arranged so that: pads (30) arranged in a plurality of rows include: first-row pads (30a) connected to first metal wires (10a) among metal wires (10); and second-row pads (30b) connected to second metal wires (10b) among the metal wires (10), the first metal wires (10a) being longer than the second metal wires (10b); and that each of the first connecting lines (10a) is formed so as to be separated from a corresponding one of the second-row pads (30b) by at least an insulating layer, and so as to extend not through a region between the corresponding second-row pad (30b) and a second-row pad (30b) adjacent to the corresponding second-row pad (30b), but through a region below the corresponding second-row pad (30b).

Abstract: A wiring board of the present invention (1) is arranged so that: pads (30) arranged in a plurality of rows include: first-row pads (30a) connected to first metal wires (10a) among metal wires (10); and second-row pads (30b) connected to second metal wires (10b) among the metal wires (10), the first metal wires (10a) being longer than the second metal wires (10b); each of the first metal wires (10a) is formed so as to be separated from a corresponding one of the second-row pads (30b) by at least an insulating layer, and so as to have a widthwise center in a lower region below the corresponding second-row pad (30b); and each of the first metal wires (10a) has widthwise edges provided, in a plan view, beyond widthwise edges of a corresponding one of the second-row pads (30b) in a region in which the first metal wire (10a) overlaps with the corresponding second-row pad (30b).

Abstract: Provided is a semiconductor element in which decrease in reliability of wiring is suppressed. A driver IC (10) has a plurality of output bumps (12) arranged in the direction (direction A) along the long sides (11a and 11b). The output bumps include a plurality of source bumps (12a) arranged near the center section of the long side, and a plurality of gate bumps (12b) arranged towards the end portions of the long side. The source bumps are arranged close to the long side (11a), and the gate bumps are arranged closer to the long side (11b) than the source bumps.

Abstract: The present invention provides a reduced size electronic circuit device, a manufacturing method of the same, and a display device having the same made by the manufacturing method. The electronic circuit device of the present invention is an electronic circuit device, wherein a first electronic component and a second electronic component are respectively connected electrically to a third electronic component; the first electronic component is bonded to the third electronic component through a first adhesive layer; the second electronic component is bonded to the third electronic component through the first and second adhesive layers; and one of the first adhesive layer and the second adhesive layer contains an anisotropic conductive material and the other adhesive layer does not contain the anisotropic conductive material.

Abstract: A liquid crystal display device (100) includes a glass substrate (110) having an LSI chip (130) and an FPC board (140) mounted thereon. A component ACF (150a) made of a single sheet is used to further mount discrete electronic components such as stabilizing capacitors (150) on the glass substrate (110). The component ACF (150a) has a size that covers not only a region where the discrete electronic components are to be mounted, but also the top surfaces of the LSI chip (130) and the FPC board (140) which are mounted first. By thus using the large component ACF (150a), a positional constraint upon adhering the component ACF (150a) to the glass substrate (110) is eliminated, reducing the area of a region where the discrete electronic components are mounted. By this, a board module miniaturized by reducing the area of a region where discrete electronic components are mounted is provided.

Abstract: In a liquid crystal display device (10), stabilizing capacitors (61), bypass capacitors (62) and boosting capacitors (63), which would conventionally be mounted on an FPC board (50), are disposed along long and short input sides of an LSI chip (40) mounted on a projection (20a) of a glass substrate (20) and the capacitors are connected to their respective input terminals of the LSI chip (40) via capacitor traces (71). This makes it possible to narrow the FPC board (50) connected to the liquid crystal display device (10), thereby achieving size reduction of the liquid crystal display device (10) while achieving reduction in manufacturing cost, including processing and material cost of the FPC board (50).

Abstract: The present invention provides a display panel in which, without providing connection terminals, the number of which corresponds to the number of test terminals of a liquid crystal panel, on a circuit board such as an FPC board, miniaturization is obtained while reducing costs such as the mounting cost and material cost of the circuit board, and stable operation is performed. A liquid crystal panel (10) has a configuration in which jumper resistors (60a) to (60f) are provided in an overhanging portion (20a) of a glass substrate (20) to ground test terminals, which eliminates the need to ground the test terminals on an FPC board (50). Thus, wiring lines and connection terminals which are connected to the test terminals, respectively, and the numbers of which are equal to the number of the test terminals do not need to be provided on the FPC board (50), reducing the width of the FPC board (50).

Abstract: A drive IC chip (21) including a circuit for driving a display region (41) is mounted on a panel substrate (11). An anisotropic conductive film (31) is interposed between the panel substrate (11) and the drive IC chip (21) and electrically connects the bump electrodes (22) of the drive IC chip (21) and the electrode pads (27) of the panel substrate (11). The anisotropic conductive film (31) is arranged to extend beyond all side surfaces (21b to 21d) other than one specific side surface (21a) of the drive IC chip (21).