Patents by Inventor Motonobu Takeya

Motonobu Takeya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060273326
    Abstract: A semiconductor light emitting device made of nitride III-V compound semiconductors includes an active layer made of a first nitride III-V compound semiconductor containing In and Ga, such as InGaN; an intermediate layer made of a second nitride III-V compound semiconductor containing In and Ga and different from the first nitride III-V compound semiconductor, such as InGaN; and a cap layer made of a third nitride III-V compound semiconductor containing Al and Ga, such as p-type AlGaN, which are deposited in sequential contact.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 7, 2006
    Inventors: Osamu Goto, Takeharu Asano, Yasuhiko Suzuki, Motonobu Takeya, Katsuyoshi Shibuya, Takashi Mizuno, Tsuyoshi Tojo, Shiro Uchida, Masao Ikeda
  • Patent number: 7125732
    Abstract: In a semiconductor light emitting device such as a semiconductor laser using nitride III-V compound semiconductors and having a structure interposing an active layer between an n-side cladding layer and a p-side cladding layer, the p-side cladding layer is made of an undoped or n-type first layer 9 and a p-type second layer 12 that are deposited sequentially from nearer to remoter from the active layer. The first layer 9 is not thinner than 50 nm. The p-type second layer 12 includes a p-type third layer having a larger band gap inserted therein as an electron blocking layer. Thus the semiconductor light emitting device is reduced in operation voltage while keeping a thickness of the p-side cladding layer necessary for ensuring favorable optical properties.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: October 24, 2006
    Assignee: Sony Corporation
    Inventors: Motonobu Takeya, Takeharu Asano, Masao Ikeda
  • Publication number: 20060192209
    Abstract: An optical integrated semiconductor light emitting device with improved light emitting efficiency is provided by preventing leak current from flowing through a high defect region of the substrate. The optical integrated semiconductor light emitting device includes: a substrate, in which in a low defect region made of crystal having a first average dislocation density, one or more high defect regions having a second average dislocation density higher than the first average dislocation density are included; and a Group III-V nitride semiconductor layer which is formed on the substrate, has a plurality of light emitting device structures, and has a groove in the region including the region corresponding to the high defect region (high defect region).
    Type: Application
    Filed: January 31, 2006
    Publication date: August 31, 2006
    Inventors: Osamu Maeda, Tsuyoshi Fujimoto, Motonobu Takeya, Toshihiro Hashidu, Masaki Shiozaki, Yoshio Oofuji
  • Patent number: 7026179
    Abstract: When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0<y/x?0.011 and x?450 ?m. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0<H?70×10?4 (cm), and Z=y/x, D is controlled to satisfy the relation 0<D<(2/CZ)cos?1(1?HCZ), where C (cm?1) is the proportionality constant when the radius of curvature of the substrate ? (cm) is expressed as 1/?=CZ.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: April 11, 2006
    Assignee: Sony Corporation
    Inventors: Yasuhiko Suzuki, Takeharu Asano, Motonobu Takeya, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya
  • Patent number: 6995406
    Abstract: In a multi-beam semiconductor laser including nitride III–V compound semiconductor layers stacked on one surface of a substrate of sapphire or other material to form laser structures, and including a plurality of anode electrodes and a plurality of cathode electrodes formed on the nitride III–V compound semiconductor layers, one of the anode electrodes is formed to bridge over one of the cathode electrodes via an insulating film, and another anode electrode is formed to bridge over another of the cathode electrodes via an insulating film.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: February 7, 2006
    Inventors: Tsuyoshi Tojo, Yoshifumi Yabuki, Shinichi Ansai, Tomonori Hino, Osamu Goto, Tsuyoshi Fujimoto, Osamu Matsumoto, Motonobu Takeya, Yoshio Oofuji
  • Patent number: 6991952
    Abstract: Provided is a method of manufacturing a semiconductor device, which is adapted to prevent the deposition of a material on a laser light emitting edge, thereby enabling an improvement in longevity characteristics of a laser. A base having a laser chip mounted thereon is irradiated with an energy beam having a shorter wavelength than an oscillation wavelength of the laser chip. Photolysis and oxidation caused by the energy beam cause the removal of an adherent from the overall base or the deterioration thereof, and incidentally, the adherent is derived from an adhesive sheet used to attach the laser chip to the base, or the like. Preferably, laser light or ultraviolet light, for example, is used as the energy beam. Alternatively, the base having the laser chip mounted thereon may be irradiated with plasma so as to remove the adherent utilizing an ion cleaning effect of the plasma. After irradiation, a top is mounted to the base so as to shut off the laser chip from the outside.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: January 31, 2006
    Assignee: Sony Corporation
    Inventors: Takashi Mizuno, Motonobu Takeya, Takeharu Asano, Masao Ikeda
  • Patent number: 6972206
    Abstract: Provided is a nitride semiconductor having a larger low-defective region on a surface thereof, a semiconductor device using the nitride semiconductor, a method of manufacturing a nitride semiconductor capable of easily reducing surface defects in a step of forming a layer through lateral growth, and a method of manufacturing a semiconductor device manufactured by the use of the nitride semiconductor. A seed crystal portion is formed into stripes on a substrate with a buffer layer sandwiched therebetween. Then, a crystal is grown from the seed crystal portion in two steps of growth conditions to form a nitride semiconductor layer. In a first step, a low temperature growth portion having a trapezoidal-shaped cross section in a layer thickness direction is formed at a growth temperature of 1030° C., and in a second step, lateral growth predominantly takes place at a growth temperature of 1070° C. Then, a high temperature growth potion is formed between the low temperature growth portions.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: December 6, 2005
    Assignee: Sony Corporation
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima
  • Patent number: 6939730
    Abstract: Provided is a nitride semiconductor having a larger low-defective region on a surface thereof, a semiconductor device using the nitride semiconductor, a method of manufacturing a nitride semiconductor capable of easily reducing surface defects in a step of forming a layer through lateral growth, and a method of manufacturing a semiconductor device manufactured by the use of the nitride semiconductor. A seed crystal portion is formed into stripes on a substrate with a buffer layer sandwiched therebetween. Then, a crystal is grown from the seed crystal portion in two steps of growth conditions to form a nitride semiconductor layer. In a first step, a low temperature growth portion having a trapezoidal-shaped cross section in a layer thickness direction is formed at a growth temperature of 1030° C., and in a second step, lateral growth predominantly takes place at a growth temperature of 1070° C. Then, a high temperature growth potion is formed between the low temperature growth portions.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: September 6, 2005
    Assignee: Sony Corporation
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima
  • Publication number: 20050191773
    Abstract: When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0<y/x?0.011 and x?450 ?m. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0<H?70×10?4 (cm), and Z=y/x, D is controlled to satisfy the relation 0<D<(2/CZ)cos?1(1?HCZ), where C (cm?1) is the proportionality constant when the radius of curvature of the substrate ? (cm) is expressed as 1/?=CZ.
    Type: Application
    Filed: June 23, 2004
    Publication date: September 1, 2005
    Inventors: Yasuhiko Suzuki, Takeharu Asano, Motonobu Takeya, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya
  • Publication number: 20050178471
    Abstract: Provided is a nitride semiconductor having a larger low-defective region on a surface thereof, a semiconductor device using the nitride semiconductor, a method of manufacturing a nitride semiconductor capable of easily reducing surface defects in a step of forming a layer through lateral growth, and a method of manufacturing a semiconductor device manufactured by the use of the nitride semiconductor. A seed crystal portion is formed into stripes on a substrate with a buffer layer sandwiched therebetween. Then, a crystal is grown from the seed crystal portion in two steps of growth conditions to form a nitride semiconductor layer. In a first step, a low temperature growth portion having a trapezoidal-shaped cross section in a layer thickness direction is formed at a growth temperature of 1030° C., and in a second step, lateral growth predominantly takes place at a growth temperature of 1070° C. Then, a high temperature growth potion is formed between the low temperature growth portions.
    Type: Application
    Filed: April 18, 2005
    Publication date: August 18, 2005
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima
  • Publication number: 20050164418
    Abstract: Provided is a nitride semiconductor having a larger low-defective region on a surface thereof, a semiconductor device using the nitride semiconductor, a method of manufacturing a nitride semiconductor capable of easily reducing surface defects in a step of forming a layer through lateral growth, and a method of manufacturing a semiconductor device manufactured by the use of the nitride semiconductor. A seed crystal portion is formed into stripes on a substrate with a buffer layer sandwiched therebetween. Then, a crystal is grown from the seed crystal portion in two steps of growth conditions to form a nitride semiconductor layer. In a first step, a low temperature growth portion having a trapezoidal-shaped cross section in a layer thickness direction is formed at a growth temperature of 1030° C., and in a second step, lateral growth predominantly takes place at a growth temperature of 1070° C. Then, a high temperature growth potion is formed between the low temperature growth portions.
    Type: Application
    Filed: March 22, 2005
    Publication date: July 28, 2005
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima
  • Publication number: 20050098791
    Abstract: A nitride semiconductor having a large low-defect region in a surface thereof, and a semiconductor device using the same are provided. Also, a manufacturing method for a nitride semiconductor comprising a layer formation step using a transverse growth technique where surface defects can easily be reduced, and a manufacturing method for a semiconductor device using the same are provided. On a substrate, a seed crystal part is formed in a stripe pattern with a buffer layer in between. Next, crystals are grown from the seed crystal part in two stages of growth conditions to form a nitride semiconductor layer. Low temperature growing parts with a trapezoid shaped cross section are formed at a growth temperature of 1030° C. in the first stage and a transverse growth is dominantly advanced at a growth temperature of 1070° C. to form a high temperature growing part between the low temperature growing parts in the second stage.
    Type: Application
    Filed: December 2, 2004
    Publication date: May 12, 2005
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima, Shinro Ikeda, Katsuyoshi Shibuya, Yasuhiko Suzuki
  • Patent number: 6890785
    Abstract: A nitride semiconductor having a large low-defect region in a surface thereof, and a semiconductor device using the same are provided. Also, a manufacturing method for a nitride semiconductor comprising a layer formation step using a transverse growth technique where surface defects can easily be reduced, and a manufacturing method for a semiconductor device using the same are provided. On a substrate, a seed crystal part is formed in a stripe pattern with a buffer layer in between. Next, crystals are grown from the seed crystal part in two stages of growth conditions to form a nitride semiconductor layer. Low temperature growing parts with a trapezoid shaped cross section are formed at a growth temperature of 1030° C. in the first stage and a transverse growth is dominantly advanced at a growth temperature of 1070° C. to form a high temperature growing part between the low temperature growing parts in the second stage.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: May 10, 2005
    Assignee: Sony Corporation
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima, Shinro Ikeda, Katsuyoshi Shibuya, Yasuhiko Suzuki
  • Patent number: 6870193
    Abstract: In a semiconductor light emitting device such as a semiconductor laser using nitride III-V compound semiconductors and having a structure interposing an active layer between an n-side cladding layer and a p-side cladding layer, the p-side cladding layer is made of an undoped or n-type first layer 9 and a p-type second layer 12 that are deposited sequentially from nearer to remoter from the active layer. The first layer 9 is not thinner than 50 nm. The p-type second layer 12 includes a p-type third layer having a larger band gap inserted therein as an electron blocking layer. Thus the semiconductor light emitting device is reduced in operation voltage while keeping a thickness of the p-side cladding layer necessary for ensuring favorable optical properties.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: March 22, 2005
    Assignee: Sony Corporation
    Inventors: Motonobu Takeya, Takeharu Asano, Masao Ikeda
  • Patent number: 6861340
    Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: March 1, 2005
    Assignee: Sony Corporation
    Inventor: Motonobu Takeya
  • Publication number: 20050040409
    Abstract: In a semiconductor light emitting device such as a semiconductor laser using nitride III-V compound semiconductors and having a structure interposing an active layer between an n-side cladding layer and a p-side cladding layer, the p-side cladding layer is made of an undoped or n-type first layer 9 and a p-type second layer 12 that are deposited sequentially from nearer to remoter from the active layer. The first layer 9 is not thinner than 50 nm. The p-type second layer 12 includes a p-type third layer having a larger band gap inserted therein as an electron blocking layer. Thus the semiconductor light emitting device is reduced in operation voltage while keeping a thickness of the p-side cladding layer necessary for ensuring favorable optical properties.
    Type: Application
    Filed: September 2, 2004
    Publication date: February 24, 2005
    Inventors: Motonobu Takeya, Takeharu Asano, Masao Ikeda
  • Publication number: 20050023541
    Abstract: In a semiconductor light emitting device such as a semiconductor laser using nitride III-V compound semiconductors and having a structure interposing an active layer between an n-side cladding layer and a p-side cladding layer, the p-side cladding layer is made of an undoped or n-type first layer 9 and a p-type second layer 12 that are deposited sequentially from nearer to remoter from the active layer. The first layer 9 is not thinner than 50 nm. The p-type second layer 12 includes a p-type third layer having a larger band gap inserted therein as an electron blocking layer. Thus the semiconductor light emitting device is reduced in operation voltage while keeping a thickness of the p-side cladding layer necessary for ensuring favorable optical properties.
    Type: Application
    Filed: August 30, 2004
    Publication date: February 3, 2005
    Inventors: Motonobu Takeya, Takeharu Asano, Masao Ikeda
  • Publication number: 20050000407
    Abstract: A semiconductor laser, a semiconductor device and a nitride series III-V group compound substrate capable of obtaining a crystal growth layer with less fluctuation of the crystallographic axes and capable of improving the device characteristics, as well as a manufacturing method therefor are provided. The semiconductor laser comprises, on one surface of a substrate used for growing, a plurality of spaced apart seed crystal layers and an n-side contact layer having a lateral growing region which is grown on the basis of the plurality of seed crystal layers. The seed crystal layer is formed in that a product of width w1 (unit: ?m) at the boundary thereof relative to the n-side contact layer along the arranging direction A and a thickness t1 (unit: ?m) along the direction of laminating the n-side contact layer is 15 or less. This can decrease the fluctuation of the crystallographic axes in the n-side contact layer.
    Type: Application
    Filed: August 2, 2004
    Publication date: January 6, 2005
    Inventors: Motonobu Takeya, Katsunori Yanashima, Takeharu Asano, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya, Tomonori Hino, Satoru Kijima, Masao Ikeda
  • Patent number: 6836498
    Abstract: A semiconductor laser, a semiconductor device and a nitride series III-V group compound substrate capable of obtaining a crystal growth layer with less fluctuation of the crystallographic axes and capable of improving the device characteristics, as well as a manufacturing method therefor are provided. The semiconductor laser comprises, on one surface of a substrate used for growing, a plurality of spaced apart seed crystal layers and an n-side contact layer having a lateral growing region which is grown on the basis of the plurality of seed crystal layers. The seed crystal layer is formed in that a product of width w1 (unit: &mgr;m) at the boundary thereof relative to the n-side contact layer along the arranging direction A and a thickness t1 (unit: &mgr;m) along the direction of laminating the n-side contact layer is 15 or less. A semiconductor layer comprising a nitride series III-V group compound semiconductor is laminated on a substrate 11 comprising an n-type GaN.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: December 28, 2004
    Assignee: Sony Corporation
    Inventors: Motonobu Takeya, Katsunori Yanashima, Takeharu Asano, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya, Tomonori Hino, Satoru Kijima, Masao Ikeda
  • Patent number: 6829270
    Abstract: When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0<y/x≦0.011 and x≧450 &mgr;m. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0<H≦70×10−4 (cm), and Z=y/x, D is controlled to satisfy the relation 0<D<(2/CZ)cos−1(1−HCZ), where C (cm−1) is the proportionality constant when the radius of curvature of the substrate &rgr; (cm) is expressed as 1/&rgr;=CZ.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: December 7, 2004
    Assignee: Sony Corporation
    Inventors: Yasuhiko Suzuki, Takeharu Asano, Motonobu Takeya, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya