Patents by Inventor Motoo Suwa
Motoo Suwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10886695Abstract: Improve semiconductor device performance. The wiring WL1A on which the semiconductor chip CHP1 in which the semiconductor lasers LD is formed is mounted has a stub STB2 in the vicinity of the mounting area of the semiconductor chip CHP1.Type: GrantFiled: August 19, 2019Date of Patent: January 5, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuaki Tsuchiyama, Motoo Suwa, Hidemasa Takahashi
-
Patent number: 10809470Abstract: A performance of an electronic device is improved. An optical transceiver (electronic device) includes a semiconductor device electrically connected to a transmission line. In this semiconductor device, a resistor is arranged between a wiring electrically connected to the transmission line and a semiconductor chip having a semiconductor laser formed therein.Type: GrantFiled: May 13, 2019Date of Patent: October 20, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuaki Tsuchiyama, Motoo Suwa, Ryuichi Oikawa
-
Patent number: 10726878Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.Type: GrantFiled: June 18, 2018Date of Patent: July 28, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
-
Publication number: 20200083663Abstract: Improve semiconductor device performance. The wiring WL1A on which the semiconductor chip CHP1 in which the semiconductor lasers LD is formed is mounted has a stub STB2 in the vicinity of the mounting area of the semiconductor chip CHP1.Type: ApplicationFiled: August 19, 2019Publication date: March 12, 2020Inventors: Kazuaki TSUCHIYAMA, Motoo SUWA, Hidemasa TAKAHASHI
-
Publication number: 20190377143Abstract: A performance of an electronic device is improved. An optical transceiver (electronic device) includes a semiconductor device electrically connected to a transmission line. In this semiconductor device, a resistor is arranged between a wiring electrically connected to the transmission line and a semiconductor chip having a semiconductor laser formed therein.Type: ApplicationFiled: May 13, 2019Publication date: December 12, 2019Inventors: Kazuaki TSUCHIYAMA, Motoo SUWA, Ryuichi OIKAWA
-
Patent number: 10460792Abstract: To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.Type: GrantFiled: May 10, 2018Date of Patent: October 29, 2019Assignee: Renesas Electronics CorporationInventors: Motoo Suwa, Takafumi Betsui
-
Patent number: 10446531Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line.Type: GrantFiled: September 26, 2014Date of Patent: October 15, 2019Assignee: Renesas Electronics CorporationInventors: Takafumi Betsui, Motoo Suwa
-
Patent number: 10153245Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed.Type: GrantFiled: October 27, 2017Date of Patent: December 11, 2018Assignee: Renesas Electronics CorporationInventors: Takafumi Betsui, Motoo Suwa
-
Publication number: 20180301172Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.Type: ApplicationFiled: June 18, 2018Publication date: October 18, 2018Inventors: Takafumi BETSUI, Naoto TAOKA, Motoo SUWA, Shigezumi MATSUI, Norihiko SUGITA, Yoshiharu FUKUSHIMA
-
Publication number: 20180261274Abstract: To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.Type: ApplicationFiled: May 10, 2018Publication date: September 13, 2018Applicant: Renesas Electronics CorporationInventors: Motoo SUWA, Takafumi BETSUI
-
Patent number: 10043755Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. The semiconductor device includes a second wiring substrate having a plurality of terminals, a plurality of first semiconductor chips mounted on the second wiring substrate, and a second semiconductor chip mounted on the second wiring substrate. The first wiring substrate includes a first power supply line and a second power supply line supplying a plurality of power supply potentials, whose types are different from each other, to the second semiconductor chip. In a plan view, the second power supply line is arranged to cross over a first substrate side of the second wiring substrate and a first chip side of the second semiconductor chip. In a plan view, the first power supply line is arranged to pass between the second power supply line and a part of the plurality of first semiconductor chips and to extend toward a region overlapping with the second semiconductor chip.Type: GrantFiled: June 26, 2015Date of Patent: August 7, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takafumi Betsui, Motoo Suwa
-
Publication number: 20180204827Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line.Type: ApplicationFiled: September 26, 2014Publication date: July 19, 2018Applicant: Renesas Electronics CorporationInventors: Takafumi BETSUI, Motoo SUWA
-
Patent number: 10020028Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.Type: GrantFiled: November 15, 2016Date of Patent: July 10, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
-
Patent number: 9997231Abstract: An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.Type: GrantFiled: September 20, 2017Date of Patent: June 12, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toru Hayashi, Motoo Suwa
-
Patent number: 9990981Abstract: To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.Type: GrantFiled: June 9, 2016Date of Patent: June 5, 2018Assignee: Renesas Electronics CorporationInventors: Motoo Suwa, Takafumi Betsui
-
Publication number: 20180068971Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Applicant: Renesas Electronics CorporationInventors: Takafumi BETSUI, Motoo SUWA
-
Publication number: 20180033731Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. The semiconductor device includes a second wiring substrate having a plurality of terminals, a plurality of first semiconductor chips mounted on the second wiring substrate, and a second semiconductor chip mounted on the second wiring substrate. The first wiring substrate includes a first power supply line and a second power supply line supplying a plurality of power supply potentials, whose types are different from each other, to the second semiconductor chip. In a plan view, the second power supply line is arranged to cross over a first substrate side of the second wiring substrate and a first chip side of the second semiconductor chip. In a plan view, the first power supply line is arranged to pass between the second power supply line and a part of the plurality of first semiconductor chips and to extend toward a region overlapping with the second semiconductor chip.Type: ApplicationFiled: June 26, 2015Publication date: February 1, 2018Inventors: Takafumi BETSUI, Motoo SUWA
-
Publication number: 20180012645Abstract: An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.Type: ApplicationFiled: September 20, 2017Publication date: January 11, 2018Inventors: Toru HAYASHI, Motoo SUWA
-
Patent number: 9831209Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed.Type: GrantFiled: May 31, 2016Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventors: Takafumi Betsui, Motoo Suwa
-
Patent number: 9805785Abstract: An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.Type: GrantFiled: May 8, 2017Date of Patent: October 31, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toru Hayashi, Motoo Suwa