Patents by Inventor Motoo Suwa

Motoo Suwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9792959
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: October 17, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Publication number: 20170243630
    Abstract: An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.
    Type: Application
    Filed: May 8, 2017
    Publication date: August 24, 2017
    Inventors: Toru HAYASHI, Motoo SUWA
  • Patent number: 9704559
    Abstract: An electronic device includes a mounting substrate, a first semiconductor component including a first semiconductor chip that operates in synchronization with a first clock signal and being mounted on a first semiconductor component mounting area of the mounting substrate, a second semiconductor component including a second semiconductor chip that operates in synchronization with a second clock signal and being mounted on a second semiconductor component mounting area of the mounting substrate, the second semiconductor component mounting area being next to the first semiconductor component mounting area, and a third semiconductor component including a third semiconductor chip that controls the first and second semiconductor chips and being mounted on a third semiconductor component mounting area of the mounting substrate, the third semiconductor component mounting area being next to the first and the second semiconductor component mounting areas.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: July 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toru Hayashi, Motoo Suwa
  • Publication number: 20170062021
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Application
    Filed: November 15, 2016
    Publication date: March 2, 2017
    Inventors: Takafumi BETSUI, Naoto TAOKA, Motoo SUWA, Shigezumi MATSUI, Norihiko SUGITA, Yoshiharu FUKUSHIMA
  • Publication number: 20170062020
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Application
    Filed: November 15, 2016
    Publication date: March 2, 2017
    Inventors: Takafumi BETSUI, Naoto TAOKA, Motoo SUWA, Shigezumi MATSUI, Norihiko SUGITA, Yoshiharu FUKUSHIMA
  • Publication number: 20170033070
    Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed.
    Type: Application
    Filed: May 31, 2016
    Publication date: February 2, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Takafumi BETSUI, Motoo SUWA
  • Publication number: 20170032834
    Abstract: The number of terminals included in a semiconductor device which is included in an electronic device is reduced. The electronic device includes: a first semiconductor device having first and second input terminals; a second semiconductor device having a first output terminal and a first driver circuit to drive the first output terminal; and a wiring substrate over which the first and second semiconductor devices are mounted. The first and second input terminals are commonly coupled to the first output terminal via a first line formed on the wiring substrate. A composite resistance value of first and second termination resistors coupled to the first and second input terminals, respectively, is equivalent to a drive impedance of the first driver circuit.
    Type: Application
    Filed: June 1, 2016
    Publication date: February 2, 2017
    Inventors: Motoo SUWA, Takafumi BETSUI, Masato SUZUKI
  • Publication number: 20170032832
    Abstract: To provide an electronic device capable of improving a signal quality. The electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.
    Type: Application
    Filed: June 9, 2016
    Publication date: February 2, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Motoo SUWA, Takafumi BETSUI
  • Patent number: 9558806
    Abstract: The number of terminals included in a semiconductor device which is included in an electronic device is reduced. The electronic device includes: a first semiconductor device having first and second input terminals; a second semiconductor device having a first output terminal and a first driver circuit to drive the first output terminal; and a wiring substrate over which the first and second semiconductor devices are mounted. The first and second input terminals are commonly coupled to the first output terminal via a first line formed on the wiring substrate. A composite resistance value of first and second termination resistors coupled to the first and second input terminals, respectively, is equivalent to a drive impedance of the first driver circuit.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Motoo Suwa, Takafumi Betsui, Masato Suzuki
  • Patent number: 9549461
    Abstract: To improve electric characteristics of an electronic device. An electronic device includes a semiconductor device and a three-terminal capacitor mounted on the upper surface of a mounting substrate, the semiconductor device includes a power supply pad and a ground pad, the power supply pad and the ground pad are electrically connected with a power supply land and a ground land, respectively, and the power supply land and the ground land are allocated to a land line in an outermost periphery of the semiconductor device, Then, the power supply land and the ground land are electrically connected to the three-terminal capacitor by wirings formed on the upper surface of the mounting substrate.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 17, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masahiro Toyama, Motoo Suwa
  • Patent number: 9530457
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: December 27, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Patent number: 9390766
    Abstract: There is a need to provide a semiconductor device and an electronic device capable of easily allowing a bypass capacitor to always improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states. There is provided a specified signal path that connects a control chip and a memory chip mounted on a mounting substrate and transmits a reference potential generated from the control chip. A bypass capacitor is connected to the specified signal path only at a connecting part where a distance from a reference potential pad of the memory chip to the connecting part along the specified signal path is shorter than a distance from a reference potential pad of the control chip to the connecting part along the specified signal path.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 12, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuhiko Hiranuma
  • Patent number: 9158717
    Abstract: There is a need to alleviate or reduce crosstalk between bonding wires or wires in a device substrate. One selection configuration divides a multiplexed terminal group into three groups according to functions differently from another selection configuration that divides the multiplexed terminal group into two groups. A first multi-pin semiconductor device is configured such that the groups are successively arranged along one edge of the chip. The first semiconductor device connects with a second semiconductor device via a multiplexed terminal group. The multiplexed terminal group includes first through third interface terminal groups that differ from each other in signal input/output configurations.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: October 13, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Yoshikawa, Motoo Suwa
  • Publication number: 20150234758
    Abstract: There is a need to alleviate or reduce crosstalk between bonding wires or wires in a device substrate. One selection configuration divides a multiplexed terminal group into three groups according to functions differently from another selection configuration that divides the multiplexed terminal group into two groups. A first multi-pin semiconductor device is configured such that the groups are successively arranged along one edge of the chip. The first semiconductor device connects with a second semiconductor device via a multiplexed terminal group. The multiplexed terminal group includes first through third interface terminal groups that differ from each other in signal input/output configurations.
    Type: Application
    Filed: April 24, 2015
    Publication date: August 20, 2015
    Inventors: Yasuhiro YOSHIKAWA, Motoo SUWA
  • Publication number: 20150237731
    Abstract: To improve electric characteristics of an electronic device. An electronic device includes a semiconductor device and a three-terminal capacitor mounted on the upper surface of a mounting substrate, the semiconductor device includes a power supply pad and a ground pad, the power supply pad and the ground pad are electrically connected with a power supply land and a ground land, respectively, and the power supply land and the ground land are allocated to a land line in an outermost periphery of the semiconductor device, Then, the power supply land and the ground land are electrically connected to the three-terminal capacitor by wirings formed on the upper surface of the mounting substrate.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 20, 2015
    Inventors: Masahiro TOYAMA, Motoo SUWA
  • Patent number: 9087160
    Abstract: There is a need to alleviate or reduce crosstalk between bonding wires or wires in a device substrate. One selection configuration divides a multiplexed terminal group into three groups according to functions differently from another selection configuration that divides the multiplexed terminal group into two groups. A first multi-pin semiconductor device is configured such that the groups are successively arranged along one edge of the chip. The first semiconductor device connects with a second semiconductor device via a multiplexed terminal group. The multiplexed terminal group includes first through third interface terminal groups that differ from each other in signal input/output configurations.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: July 21, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Yoshikawa, Motoo Suwa
  • Publication number: 20150043298
    Abstract: To alleviate the effect of undesired signal reflection in a branch wiring, even when the length of a branch path branched from a main wiring of a fly-by topology is long. On a mounting substrate on which a plurality of first semiconductor components that operate in synchronization with a clock signal and a second semiconductor component that controls the first semiconductor components, a plurality of main wirings and branch wirings branched at a plurality of branch points of each of the main wirings are provided as signal paths that electrically couple the second semiconductor component with the first semiconductor components. A chip resistor is coupled in series in the midway of branch wirings that reach a corresponding first semiconductor component from the branch points which do not overlap the first semiconductor, component and which are located away from the first semiconductor component.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 12, 2015
    Inventors: Toru Hayashi, Motoo Suwa
  • Publication number: 20150036406
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Application
    Filed: October 21, 2014
    Publication date: February 5, 2015
    Inventors: Takafumi BETSUI, Naoto TAOKA, Motoo SUWA, Shigezumi MATSUI, Norihiko SUGITA, Yoshiharu FUKUSHIMA
  • Patent number: 8898613
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: November 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Publication number: 20140160826
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takafumi BETSUI, Naoto TAOKA, Motoo SUWA, Shigezumi MATSUI, Norihiko SUGITA, Yoshiharu FUKUSHIMA