Patents by Inventor Motoo Suwa
Motoo Suwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140115199Abstract: There is a need to alleviate or reduce crosstalk between bonding wires or wires in a device substrate. One selection configuration divides a multiplexed terminal group into three groups according to functions differently from another selection configuration that divides the multiplexed terminal group into two groups. A first multi-pin semiconductor device is configured such that the groups are successively arranged along one edge of the chip. The first semiconductor device connects with a second semiconductor device via a multiplexed terminal group. The multiplexed terminal group includes first through third interface terminal groups that differ from each other in signal input/output configurations.Type: ApplicationFiled: October 23, 2013Publication date: April 24, 2014Applicant: Renesas Electronics CorporationInventors: Yasuhiro Yoshikawa, Motoo Suwa
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Patent number: 8694949Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.Type: GrantFiled: January 23, 2013Date of Patent: April 8, 2014Assignee: Renesas Electronics CorporationInventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
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Patent number: 8581302Abstract: Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.Type: GrantFiled: November 12, 2011Date of Patent: November 12, 2013Assignee: Renesas Electronics CorporationInventors: Mitsuya Kinoshita, Motoo Suwa, Akinobu Watanabe, Shigezumi Matsui
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Patent number: 8526267Abstract: To suppress a timing window from being narrowed undesirably by the harmonic component of a signal output from a semiconductor component without imposing a burden on the semiconductor component that controls access. A capacitor element is arranged in series with a specific transmission path branching from a predetermined node of a signal transmission path and reaching to a ground plane, the signal transmission path supplying an enable control signal that indicates the validity of a clock signal and a command and address signal output from a semiconductor component that controls access on a substrate to another semiconductor component to be accessed on the substrate. The capacitor element functions as a short-circuit path to the ground plane for the harmonic component of the enable control signal and makes smaller the through rate and makes larger the timing window of the enable control signal compared to those when the capacitor element is not provided.Type: GrantFiled: June 28, 2011Date of Patent: September 3, 2013Assignee: Renesas Electronics CorporationInventors: Motoo Suwa, Toshikazu Matsuda
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Patent number: 8386992Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.Type: GrantFiled: December 2, 2011Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
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Publication number: 20120206954Abstract: There is a need to provide a semiconductor device and an electronic device capable of easily allowing a bypass capacitor to always improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states. There is provided a specified signal path that connects a control chip and a memory chip mounted on a mounting substrate and transmits a reference potential generated from the control chip. A bypass capacitor is connected to the specified signal path only at a connecting part where a distance from a reference potential pad of the memory chip to the connecting part along the specified signal path is shorter than a distance from a reference potential pad of the control chip to the connecting part along the specified signal path.Type: ApplicationFiled: February 13, 2012Publication date: August 16, 2012Inventors: Yasuhiro YOSHIKAWA, Motoo Suwa, Kazuhiko Hiranuma
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Publication number: 20120126403Abstract: Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.Type: ApplicationFiled: November 12, 2011Publication date: May 24, 2012Inventors: Mitsuya KINOSHITA, Motoo Suwa, Akinobu Watanabe, Shigezumi Matsui
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Patent number: 8183688Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.Type: GrantFiled: February 8, 2011Date of Patent: May 22, 2012Assignee: Renesas Electronics CorporationInventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
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Publication number: 20120079238Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.Type: ApplicationFiled: December 2, 2011Publication date: March 29, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takafumi BETSUI, Naoto TAOKA, Motoo SUWA, Shigezumi MATSUI, Norihiko SUGITA, Yoshiharu FUKUSHIMA
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Patent number: 8091061Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.Type: GrantFiled: December 28, 2006Date of Patent: January 3, 2012Assignee: Renesas Electronics CorporationInventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
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Publication number: 20110317475Abstract: To suppress a timing window from being narrowed undesirably by the harmonic component of a signal output from a semiconductor component without imposing a burden on the semiconductor component that controls access. A capacitor element is arranged in series with a specific transmission path branching from a predetermined node of a signal transmission path and reaching to a ground plane, the signal transmission path supplying an enable control signal that indicates the validity of a clock signal and a command and address signal output from a semiconductor component that controls access on a substrate to another semiconductor component to be accessed on the substrate. The capacitor element functions as a short-circuit path to the ground plane for the harmonic component of the enable control signal and makes smaller the through rate and makes larger the timing window of the enable control signal compared to those when the capacitor element is not provided.Type: ApplicationFiled: June 28, 2011Publication date: December 29, 2011Inventors: Motoo SUWA, Toshikazu MATSUDA
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Patent number: 8053911Abstract: Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.Type: GrantFiled: September 24, 2010Date of Patent: November 8, 2011Assignee: Renesas Electronics CorporationInventors: Toru Hayashi, Motoo Suwa, Kazuo Murakami
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Publication number: 20110127671Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.Type: ApplicationFiled: February 8, 2011Publication date: June 2, 2011Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
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Patent number: 7945801Abstract: A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.Type: GrantFiled: July 9, 2008Date of Patent: May 17, 2011Assignee: Renesas Electronics CorporationInventors: Shigezumi Matsui, Takashi Sato, Kazuyuki Sakata, Tsuyoshi Yaguchi, Kenzo Kuwabara, Atsushi Nakamura, Motoo Suwa, Ryoichi Sano, Hisashi Shiota
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Patent number: 7888795Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.Type: GrantFiled: June 7, 2010Date of Patent: February 15, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
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Patent number: 7888788Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.Type: GrantFiled: August 20, 2010Date of Patent: February 15, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Yoshikawa, Motoo Suwa, Hiroshi Toyoshima
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Publication number: 20110016345Abstract: Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.Type: ApplicationFiled: September 24, 2010Publication date: January 20, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toru Hayashi, Motoo Suwa, Kazuo Murakami
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Publication number: 20100314761Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.Type: ApplicationFiled: August 20, 2010Publication date: December 16, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro Yoshikawa, Motoo Suwa, Hiroshi Toyoshima
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Patent number: 7816795Abstract: Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.Type: GrantFiled: December 23, 2008Date of Patent: October 19, 2010Assignee: Renensas Electronics CorporationInventors: Toru Hayashi, Motoo Suwa, Kazuo Murakami
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Publication number: 20100244238Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.Type: ApplicationFiled: June 7, 2010Publication date: September 30, 2010Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata