Patents by Inventor Mourad El Baraji

Mourad El Baraji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10937478
    Abstract: An apparatus includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a second MTJ having a second magnetic characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The first magnetic characteristic is based on a first magnetic anisotropy and a first offset field on a first storage layer of the first MTJ. The second magnetic characteristic is based on a second magnetic anisotropy and a second offset field on a second storage layer of the second MTJ, The apparatus further includes a metallic separator coupling the first MTJ with the second MTJ, wherein the first MTJ and the second MTJ are arranged in series.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 2, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Kadriye Deniz Bozdag, Marcin Gajek, Mourad El Baraji, Eric Michael Ryan
  • Patent number: 10930332
    Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: February 23, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Susmita Karmakar, Neal Berger, Mourad El Baraji, Benjamin Louie
  • Patent number: 10891997
    Abstract: An memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A first circuit provides a first voltage on an addressed bit line of the plurality of bit lines during a write cycle, wherein the addressed bit line corresponds to an addressed memory cell.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 12, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Mourad El Baraji, Lester Crudele, Benjamin Louie
  • Patent number: 10818330
    Abstract: The present invention is directed a method for programming multiple memory cells connected to a common word line to different resistance regimes. Each cell includes a bipolar switching memory element and an access transistor coupled in series between first and second conductive lines. The memory element and access transistor are disposed adjacent to the first and second conductive lines, respectively. The method includes the steps of applying a first voltage to the common word line to program a first group of memory cells to a first resistance regime; and after the first group of memory cells is programmed to the first resistance regime, programming a second group of memory cells to a second resistance regime by raising the potential of second conductive lines connected to the first group of memory cells to a second voltage and raising the first voltage of the common word line to a third voltage.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 27, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Thinh Tran, Mourad El Baraji
  • Publication number: 20200251155
    Abstract: The present invention is directed a method for programming multiple memory cells connected to a common word line to different resistance regimes. Each cell includes a bipolar switching memory element and an access transistor coupled in series between first and second conductive lines. The memory element and access transistor are disposed adjacent to the first and second conductive lines, respectively. The method includes the steps of applying a first voltage to the common word line to program a first group of memory cells to a first resistance regime; and after the first group of memory cells is programmed to the first resistance regime, programming a second group of memory cells to a second resistance regime by raising the potential of second conductive lines connected to the first group of memory cells to a second voltage and raising the first voltage of the common word line to a third voltage.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Inventors: Thinh Tran, Mourad El Baraji
  • Patent number: 10692569
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 23, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Michail Tzoufras, Marcin Gajek, Kadriye Deniz Bozdag, Mourad El Baraji
  • Patent number: 10656994
    Abstract: A method for correcting bit defects in an STT-MRAM memory is disclosed. The method includes reading a codeword in the STT-MRAM memory, wherein the STT-MRAM memory includes a plurality of codewords, wherein each codeword includes a plurality of redundant bits. Further, the method includes mapping defective bits in the codeword to redundant bits of the plurality of redundant bits based on a mapping scheme, wherein the mapping scheme is operable to determine a manner in which the defective bits in the codeword are to be mapped to the redundant bits. Finally, the method includes replacing the defective bits in the codeword with corresponding mapped redundant bits.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 19, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele
  • Patent number: 10628316
    Abstract: A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 21, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele, Daniel Hillman
  • Patent number: 10559338
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to program the state of a corresponding one of N cell elements of the MBC to a respective state parameter value. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 11, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Michail Tzoufras, Marcin Gajek, Kadriye Deniz Bozdag, Mourad El Baraji
  • Publication number: 20200043535
    Abstract: An apparatus includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a second MTJ having a second magnetic characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The first magnetic characteristic is based on a first magnetic anisotropy and a first offset field on a first storage layer of the first MTJ. The second magnetic characteristic is based on a second magnetic anisotropy and a second offset field on a second storage layer of the second MTJ, The apparatus further includes a metallic separator coupling the first MTJ with the second MTJ, wherein the first MTJ and the second MTJ are arranged in series.
    Type: Application
    Filed: July 9, 2019
    Publication date: February 6, 2020
    Inventors: Kadriye Deniz Bozdag, Marcin Gajek, Mourad El Baraji, Eric Michael Ryan
  • Patent number: 10546624
    Abstract: A memory device includes a write port, a read port, source lines, bit lines, and word lines orthogonal to the bit lines. The memory device also includes memory cells that can be arrayed in columns that are parallel to the bit lines and in rows that are orthogonal to the bit lines. The memory cells are configured so that a write by the write port to a first memory cell in a column associated with (e.g., parallel to) a first bit line and a read by the read port of a second memory cell in a column associated with (e.g., parallel to) a second, different bit line can be performed during overlapping time periods (e.g., at a same time or during a same clock cycle).
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 28, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Mourad El-Baraji, Neal Berger, Lester Crudele, Benjamin Louie
  • Publication number: 20200013454
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 9, 2020
    Inventors: Michail Tzoufras, Marcin Gajek, Kadriye Deniz Bozdag, Mourad El Baraji
  • Publication number: 20200013445
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to program the state of a corresponding one of N cell elements of the MBC to a respective state parameter value. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 9, 2020
    Inventors: Michail Tzoufras, Marcin Gajek, Kadriye Deniz Bozdag, Mourad El Baraji
  • Patent number: 10529439
    Abstract: A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 7, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele
  • Patent number: 10489245
    Abstract: A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: November 26, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele
  • Patent number: 10481976
    Abstract: A method for correcting bit defects in a memory array is disclosed. The method comprises determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for all bits comprising the memory array, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous. The method further comprises forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. Finally, the method comprises replacing each short-circuited memory bit-cell with a corresponding redundant bit in the codeword associated with the short-circuited memory bit-cell.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: November 19, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele
  • Publication number: 20190348097
    Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Inventors: Susmita KARMAKAR, Neal BERGER, Mourad EL BARAJI, Benjamin LOUIE
  • Patent number: 10460781
    Abstract: A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. Further, the memory device comprises an x decoder circuit coupled to the memory array for decoding an x portion of a memory address for the memory array and a y multiplexer circuit coupled to the memory array and operable to simultaneously multiplex across the memory array based on two y portions of memory addresses and, based thereon with the x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of the memory array, wherein the x decoder and the y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to the memory array.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 29, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele, Daniel Hillman
  • Patent number: 10446210
    Abstract: A memory pipeline for performing a write operation in a memory device is disclosed. The memory pipeline comprises an input register operable to receive a first data word and an associated address to be written into a memory bank. The memory pipeline also comprises a pre-read register of the first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register and further operable to pre-read a second data word stored in the memory bank at the associated address. Finally, the memory pipeline comprises a write register of the second pipe-stage operable to receive the first data word, the associated address and mask bits from the pre-read register, wherein the write register is further operable to use information from the mask bits to write the first data word into the memory bank by changing those bits in the first data word that differ from the second data word.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 15, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele, Daniel Hillman
  • Patent number: 10437723
    Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. Further, the method comprises writing a second plurality of data words and associated memory addresses into a cache memory, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The method also comprises detecting a power down signal and responsive to the power down signal, and before the memory device is powered down, processing data words of the second plurality of data words and associated memory addresses through the pipeline to write data into the memory bank. Finally, the method comprises powering down the memory device.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 8, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele, Daniel Hillman