Abstract: Dynamic redundancy registers for use with a device are disclosed. The dynamic redundancy registers allow a memory bank of the device to be operated with high write error rate (WER). A first level redundancy register (e1 register) is couple to the memory bank. The e1 register may store data words that have failed verification or have not been verified. The e1 register may transfer data words to another dynamic redundancy register (e2 register). The e1 register may transfer data words that have failed to write to a memory bank after a predetermined number of re-write attempts. The e1 register may also transfer data words upon power down.

Abstract: An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.

Abstract: An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.

Abstract: A check engine includes comparators, where each comparator has flash cells. Each comparator is configured to store at least one reference bit included in a set of reference bits defining a first pattern. Each comparator also includes an input for presenting at least one target bit included in a set of target bits defining a second pattern. Each comparator is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit. The check engine is configured such that the outputs of the comparators are combined to produce a combined output that is compared to a reference signal to determine whether there is a match between the first pattern and the second pattern.

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract: Controllable readout circuit for performing a self-referenced read operation on a memory device comprising a plurality of magnetic random access memory (MRAM) cells comprising a selecting device for selecting one of the MRAM cells, and a sense circuit for sourcing a sense current to measure the first and second resistance value; the sense circuit comprising a sample and hold circuit for performing said storing said first resistance value, and a differential amplifier circuit for performing said comparing the second resistance value to the stored first resistance value; wherein the controllable readout circuit further comprises a control circuit adapted to provide a pulse-shaped timing signal with a pulse duration controlling the duration of the first read cycle and the second read cycle. The controllable readout circuit allows for controlling the duration of the first and second read cycles after completion of the MRAM cell and readout circuit fabrication.

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract: A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

Abstract: A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract: A memory device includes magnetic random access memory (“MRAM”) cells that are electrically connected in series, each one of the MRAM cells having a storage magnetization direction and a sense magnetization direction. During a write operation, multiple ones of the MRAM cells are written in parallel by switching the storage magnetization directions of the MRAM cells. During a read operation, a particular one of the MRAM cells is read by varying the sense magnetization direction of the particular one of the MRAM cells, relative to the storage magnetization direction of the particular one of the MRAM cells.

Abstract: A memory device includes at least one magnetic random access memory cell, which includes: (1) a magnetic tunnel junction having a first end and a second end; and (2) a strap electrically coupled to the second end of the magnetic tunnel junction. The memory device also includes a bit line electrically coupled to the first end of the magnetic tunnel junction. During a write operation, the bit line is configured to apply a first heating current through the magnetic tunnel junction, and the strap is configured to apply a second heating current through the strap, such that the magnetic tunnel junction is heated to at least a threshold temperature according to the first heating current and the second heating current.

Abstract: A memory device includes: (1) multiple magnetic random access memory (“MRAM”) cells each including a first end and a second end; (2) a bit line electrically coupled to the first end of at least one of the MRAM cells; and (3) a strap electrically coupled to the second end of each one of the MRAM cells. During a write operation, the bit line is configured to apply a first heating current, and the strap is configured to apply a second heating current, such that at least one of the MRAM cells is heated to at least a threshold temperature according to the first heating current and the second heating current.

Abstract: A magnetic random access memory (“MRAM”) cell includes: (1) a first magnetic layer having a first magnetization direction and a magnetic anisotropy axis; (2) a second magnetic layer having a second magnetization direction; and (3) a spacer layer disposed between the first magnetic layer and the second magnetic layer. The MRAM cell also includes a field line magnetically coupled to the MRAM cell and configured to induce a write magnetic field along a magnetic field axis, and the magnetic anisotropy axis is tilted relative to the magnetic field axis. During a write operation, the first magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis.

Abstract: A memory device comprising: a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor; a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor; a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor; wherein the memory device further comprises a plurality of source lines, each source line connecting MRAM cells along a row; and wherein each source line connecting the MRAM cells via the other end of the magnetic tunnel junction.

Abstract: A magnetic random access memory (MRAM) cell includes a storage layer, a sense layer, and a spacer layer between the storage layer and the sense layer. A field line is magnetically coupled to the MRAM cell to induce a magnetic field along a magnetic field axis, and at least one of the storage layer and the sense layer has a magnetic anisotropy axis that is tilted relative to the magnetic field axis. During a write operation, a storage magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, where at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis. During a read operation, a sense magnetization direction is varied, relative to the storage magnetization direction, to determine the data stored by the storage layer.

Abstract: A magnetic random access memory cell includes a sense layer, a storage layer, and a spacer layer disposed between the sense layer and the storage layer. During a write operation, the storage layer has a magnetization direction that is switchable between m directions to store data corresponding to one of m logic states, with m>2. During a read operation, the sense layer has a magnetization direction that is varied, relative to the magnetization direction of the storage layer, to determine the data stored by the storage layer.

Abstract: A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption.

Abstract: A memory device includes at least one magnetic random access memory cell, which includes: (1) a magnetic tunnel junction having a first end and a second end; and (2) a strap electrically coupled to the second end of the magnetic tunnel junction. The memory device also includes a bit line electrically coupled to the first end of the magnetic tunnel junction. During a write operation, the bit line is configured to apply a first heating current through the magnetic tunnel junction, and the strap is configured to apply a second heating current through the strap, such that the magnetic tunnel junction is heated to at least a threshold temperature according to the first heating current and the second heating current.