Abstract: A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.

Abstract: According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.

Abstract: A SRAM with reduced subthreshold leakage current, the SRAM comprising a pMOSFET with its gate at VSS and its source at VCC, and a diode-connected pMOSFET with its source at VCC, where the drains of the pMOSFET and the diode-connected pMOSFET are connected together to provide a voltage VCCL, where VSS<VCCL<VCC. The beta of the diode-connected pMOSFET is substantially larger than the beta of the pMOSFET. The wordline associated with each memory cell is driven to a voltage −VEE during a read operation, where −VEE<VSS and VEE≦VCC−VCCL. Each memory cell has cross-coupled inverters to store a data bit, where the cross-coupled inverters have pMOSFETs with their sources at VCCL.

Abstract: A leakage compensation approach enabling full Vcc precharge. An array of memory cells is coupled between a pair of bit lines. A precharge circuit precharges the pair of bit lines to substantially a supply voltage level and a leakage compensation circuit supplies a first compensation current to a first one of the bit lines to substantially compensate for leakage current supplied by the first bit line during a memory access operation directed to one of the plurality of memory cells.