Patents by Inventor Mujahid Muhammad
Mujahid Muhammad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9590108Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.Type: GrantFiled: January 14, 2016Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20160284852Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.Type: ApplicationFiled: June 2, 2016Publication date: September 29, 2016Inventors: John B. CAMPI, JR., Robert J. GAUTHIER, JR., Rahul MISHRA, Souvick MITRA, Mujahid MUHAMMAD
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Patent number: 9397163Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.Type: GrantFiled: October 14, 2015Date of Patent: July 19, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20160197080Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.Type: ApplicationFiled: March 11, 2016Publication date: July 7, 2016Applicant: GlobalFoundries Inc.Inventors: John B. Campi, JR., Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20160181162Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.Type: ApplicationFiled: October 14, 2015Publication date: June 23, 2016Inventors: John B. CAMPI, JR., Robert J. GAUTHIER, JR., Rahul MISHRA, Souvick MITRA, Mujahid MUHAMMAD
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Patent number: 9349732Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.Type: GrantFiled: March 30, 2015Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20160141421Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.Type: ApplicationFiled: January 14, 2016Publication date: May 19, 2016Inventors: John B. Campi, JR., Robert J. Gauthier, JR., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20160141365Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.Type: ApplicationFiled: October 14, 2015Publication date: May 19, 2016Inventors: John B. CAMPI, JR., Robert J. GAUTHIER, JR., Rahul MISHRA, Souvick MITRA, Mujahid MUHAMMAD
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Patent number: 9281379Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.Type: GrantFiled: November 19, 2014Date of Patent: March 8, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20160036219Abstract: Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from an electrostatic discharge event at an input/output pin. The protection circuit includes a silicon-controlled rectifier having a well and an anode in the well. The anode is coupled with the input/output pin. The protection circuit further includes a control circuit coupled with the well. The control circuit is configured to supply a first control logic voltage to the well that places the silicon-controlled rectifier in a blocking state, and a second control logic voltage to the well that places the silicon-controlled rectifier in a low impedance state. When placed in its low impedance state, the silicon-controlled rectifier is configured to divert current from the electrostatic discharge event at the input/output pin away from the integrated circuit.Type: ApplicationFiled: August 1, 2014Publication date: February 4, 2016Inventors: John B. Campi, JR., Robert J. Gauthier, JR., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Patent number: 9236374Abstract: Fin contacted electrostatic discharge (ESD) devices with improved heat distribution and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate which is aligned with at least one well region in the substrate. The method further includes forming at least one electrostatic discharge (ESD) device spanning two or more of the plurality of fins. The forming of the ESD device includes forming an epitaxial material spanning the two or more of the plurality of fins and forming one or more contacts on the epitaxial material.Type: GrantFiled: January 2, 2014Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20150206880Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.Type: ApplicationFiled: March 30, 2015Publication date: July 23, 2015Inventors: John B. Campi, JR., Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20150187753Abstract: Fin contacted electrostatic discharge (ESD) devices with improved heat distribution and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate which is aligned with at least one well region in the substrate. The method further includes forming at least one electrostatic discharge (ESD) device spanning two or more of the plurality of fins. The forming of the ESD device includes forming an epitaxial material spanning the two or more of the plurality of fins and forming one or more contacts on the epitaxial material.Type: ApplicationFiled: January 2, 2014Publication date: July 2, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. CAMPI, JR., Robert J. GAUTHIER, JR., Rahul MISHRA, Souvick MITRA, Mujahid MUHAMMAD
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Patent number: 9059278Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.Type: GrantFiled: August 6, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Patent number: 9041127Abstract: The present invention is a finFET type semiconductor device using LDMOS features. The device includes a first portion of a substrate doped with a second doping type and has a first trench, second trench, and first fin. The second portion of the substrate with a first doping type includes a third trench and second fin. The second fin between the second and third trench covers a part the first portion and a part of the second portion of the substrate. A first segment of the second fin is between the second segment and second trench. A second segment covers a part of the second portion of the substrate and is between the first segment and third trench. A gate covering at least a part of the first segment and a part of the first portion and a part of the second portion of the substrate.Type: GrantFiled: May 14, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20150041890Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.Type: ApplicationFiled: August 6, 2013Publication date: February 12, 2015Applicant: International Business Machines CorporationInventors: John B. Campi, JR., Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Publication number: 20140339649Abstract: The present invention is a finFET type semiconductor device using LDMOS features. The device includes a first portion of a substrate doped with a second doping type and has a first trench, second trench, and first fin. The second portion of the substrate with a first doping type includes a third trench and second fin. The second fin between the second and third trench covers a part the first portion and a part of the second portion of the substrate. A first segment of the second fin is between the second segment and second trench. A second segment covers a part of the second portion of the substrate and is between the first segment and third trench. A gate covering at least a part of the first segment and a part of the first portion and a part of the second portion of the substrate.Type: ApplicationFiled: May 14, 2013Publication date: November 20, 2014Applicant: International Business Machines CorporationInventors: John B. Campi, JR., Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
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Patent number: 8803276Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.Type: GrantFiled: November 6, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Mujahid Muhammad
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Patent number: 8796731Abstract: A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.Type: GrantFiled: August 20, 2010Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Michel J. Abou-Khalil, Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Mujahid Muhammad
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Patent number: 8760827Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.Type: GrantFiled: April 15, 2009Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: John B. Campi, Jr., Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Mujahid Muhammad