Abstract: Integrated circuits, methods of forming integrated circuits, and methods of determining gate dielectric layer electrical thickness in integrated circuits are provided. An exemplary integrated circuit includes a semiconductor substrate including an active region and an STI structure disposed therein, adjacent to the active region. A first gate electrode structure overlies the active region and includes a first gate dielectric layer and a first gate electrode layer. A second gate electrode structure includes a second gate dielectric layer that overlies the first gate electrode layer and a second gate electrode layer that overlies the second gate dielectric layer. A source and drain region are formed in the active region, adjacent to the first gate electrode structure. First electrical interconnects are in electrical communication with the source and drain regions. A second electrical interconnect is in electrical communication with the first gate electrode layer.

Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process is performed to form components of memory cell pairs. The FEOL process forms storage gates, access gates or word lines, source/drain regions, spacers, erase gates and source line isolation dielectrics. The memory cell pair shares a common source line (SL). A SL strap opening is provided. The source line strap opening is formed between adjacent memory cell pair. The source line strap opening does not overlap the storage gate of the memory cell.

Abstract: Disclosed are an organic semiconductor element, a fabrication method thereof, woven and non-woven fabric structures therewith, and a semiconductor device therewith. The organic semiconductor element comprising an organic semiconductor layer; a linear source electrode and a linear drain electrode provided in the organic semiconductor layer and spaced apart from and parallel to each other; a linear gate electrode provided on the organic semiconductor layer to cross the linear source and drain electrodes; and an electrolyte layer in contact with the organic semiconductor layer and the linear gate electrode.

Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.

Abstract: Device and method for forming a device are presented. The method includes providing a substrate prepared with at least a memory cell region having first and second sub-regions and a logic region having input/output (I/O) region and core region. First voltage memory cell is formed in the first sub-region and second voltage memory cell is formed in the second sub-region of the memory cell region of the same substrate. The first voltage memory cell operates in a first voltage and the second voltage memory cell operates in a second voltage which is higher than the first voltage. Each of the first and second voltage memory cells includes a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Logic I/O device is formed in the I/O region and logic core device is formed in the core region.

Abstract: A controller including a case provided with at least one opened surface, a cover opening and closing the at least one opened surface, and a circuit board provided within the case and provided with a heating unit. The cover includes a cover body and a heat radiation unit in which at least a portion of the inner surface of the cover body is concave toward the circuit board so as to be closely adhered to the heating unit for the purpose of heat radiation. Thereby, heat within the controller may be effectively radiated and the lifespan of electrical devices may be extended.

Abstract: Integrated circuits, methods of forming integrated circuits, and methods of determining gate dielectric layer electrical thickness in integrated circuits are provided. An exemplary integrated circuit includes a semiconductor substrate including an active region and an STI structure disposed therein, adjacent to the active region. A first gate electrode structure overlies the active region and includes a first gate dielectric layer and a first gate electrode layer. A second gate electrode structure includes a second gate dielectric layer that overlies the first gate electrode layer and a second gate electrode layer that overlies the second gate dielectric layer. A source and drain region are formed in the active region, adjacent to the first gate electrode structure. First electrical interconnects are in electrical communication with the source and drain regions. A second electrical interconnect is in electrical communication with the first gate electrode layer.

Abstract: Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memoir), cell region. At least first and second memory cells are formed on the memory cell region. Each of the memory cells is formed by forming a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalls of the control gate. First source/drain (S/D) region is formed adjacent to the second gate and second S/D region is formed adjacent to the first gate. The first and second gates are coupled in series and the second S/D region is a common S/D) region for adjacent first and second memory cells. An erase gate is formed over the common S/D region.

Abstract: A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.

Abstract: Disclosed are an organic semiconductor element, a fabrication method thereof, woven and non-woven fabric structures therewith, and a semiconductor device therewith. The organic semiconductor element comprising an organic semiconductor layer; a linear source electrode and a linear drain electrode provided in the organic semiconductor layer and spaced apart from and parallel to each other; a linear gate electrode provided on the organic semiconductor layer to cross the linear source and drain electrodes; and an electrolyte layer in contact with the organic semiconductor layer and the linear gate electrode.

Abstract: A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.

Abstract: Disclosed herein are a cleaner and a control method thereof. The control method of the cleaner includes: supplying predetermined rearrangement power to a motor for a predetermined time period; detecting a position of a rotor using a hall sensor; and supplying start-up power according to the detected position of the rotor.

Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.

Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.

Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process is performed to form components of memory cell pairs. The FEOL process forms storage gates, access gates or word lines, source/drain regions, spacers, erase gates and source line isolation dielectrics. The memory cell pair shares a common source line (SL). A SL strap opening is provided. The source line strap opening is formed between adjacent memory cell pair. The source line strap opening does not overlap the storage gate of the memory cell.

Abstract: A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.

Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.

Abstract: A controller including a case provided with at least one opened surface, a cover opening and closing the at least one opened surface, and a circuit board provided within the case and provided with a heating unit. The cover includes a cover body and a heat radiation unit in which at least a portion of the inner surface of the cover body is concave toward the circuit board so as to be closely adhered to the heating unit for the purpose of heat radiation. Thereby, heat within the controller may be effectively radiated and the lifespan of electrical devices may be extended.

Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.

Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.