Patents by Inventor Mun Jung
Mun Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8659067Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.Type: GrantFiled: February 25, 2013Date of Patent: February 25, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo, Sanford Chu
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Publication number: 20140001538Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sung Mun JUNG, Swee Tuck WOO, Sanford CHU, Liang Choo HSIA
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Patent number: 8541273Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.Type: GrantFiled: September 23, 2010Date of Patent: September 24, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sung Mun Jung, Swee Tuck Woo, Sanford Chu, Liang Choo Hsia
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Patent number: 8383476Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.Type: GrantFiled: September 23, 2010Date of Patent: February 26, 2013Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo, Sanford Chu
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Patent number: 8383475Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.Type: GrantFiled: September 23, 2010Date of Patent: February 26, 2013Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo, Sanford Chu
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Publication number: 20130034954Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: ApplicationFiled: October 8, 2012Publication date: February 7, 2013Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
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Publication number: 20120262985Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with a primary gate and forming a charge storage layer on the substrate over the primary gate. A secondary gate electrode layer is formed on the substrate over the charge storage layer. The charge storage and secondary gate electrode layers are patterned to form first and second secondary gates on first and second sides of the primary gate.Type: ApplicationFiled: April 12, 2011Publication date: October 18, 2012Applicant: GLOBALFOUNDRIES SINGAPORE Pte. Ltd.Inventors: Ying Qian WANG, Yu CHEN, Swee Tuck WOO, Bangun INDAJANG, Sung Mun JUNG
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Patent number: 8283263Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: GrantFiled: July 5, 2006Date of Patent: October 9, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
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Publication number: 20120074537Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sung Mun JUNG, Swee Tuck WOO, Sanford CHU, Liang Choo HSIA
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Publication number: 20120074482Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sung Mun JUNG, Kian Hong LIM, Jianbo YANG, Swee Tuck WOO, Sanford CHU
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Publication number: 20120074483Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sung Mun JUNG, Kian Hong LIM, Jianbo YANG, Swee Tuck WOO, Sanford CHU
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Patent number: 8048934Abstract: A composition for acrylic artificial stone, the composition including a (meth)acrylic monomer and an inorganic material. At least one of the (meth)acrylic monomer and the inorganic material may be contained in a component generated by decomposing a polymeric (meth)acrylic resin.Type: GrantFiled: October 8, 2008Date of Patent: November 1, 2011Assignee: Cheil Industries, Inc.Inventors: Myeong Cheon Jeon, Hyeong Gyu Ahn, Jong Gap Kim, Hae Mun Jung, Seung Hwa Jeong, Bang Jun Park
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Publication number: 20100013003Abstract: An integrated circuit (IC) is disclosed. The IC comprises a substrate with a cell region defined thereon. The cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers. The IC also includes a non-volatile memory cell in the cell region. The non-volatile memory cell has an access transistor and a storage transistor. The access transistor includes an access gate with an access gate dielectric comprising a thick gate dielectric layer on the thin gate doped well. Wells for transistors with thick gate dielectric layers have a lower dopant concentration than the thin gate doped well.Type: ApplicationFiled: September 24, 2009Publication date: January 21, 2010Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaoyu CHEN, Donghua LIU, Sung Mun JUNG, Swee Tuck WOO, Rachel LOW, Louis LIM, Siow Lee CHWA
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Patent number: 7595237Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.Type: GrantFiled: April 27, 2007Date of Patent: September 29, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaoyu Chen, Donghua Liu, Sung Mun Jung, Swee Tuck Woo, Rachel Low, Louis Lim, Siow Lee Chwa
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Patent number: 7585746Abstract: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.Type: GrantFiled: July 12, 2006Date of Patent: September 8, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Sung Mun Jung, Yoke Leng Louis Lim, Sripad Nagarad, Dong Kyun Sohn, Dong Hua Liu, Xiao Yu Chen, Rachel Low
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Patent number: 7553724Abstract: The present invention relates to a method manufacturing a code address memory (CAM) cell. The present invention uses a dielectric film in which an oxide film and a nitride film between a floating gate and a control gate in a flash memory cell are stacked as a gate insulating film between a semiconductor substrate and a gate in the CAM cell. Therefore, the present invention can reduce the area of a peripheral circuit region and stably secure repaired data since the CAM cell can be stably driven at a low operating voltage and additional boosting circuit is thus not required.Type: GrantFiled: December 28, 2001Date of Patent: June 30, 2009Assignee: Hynix Semiconductor Inc.Inventors: Jum Soo Kim, Sung Mun Jung, Min Kuck Cho, Young Bok Lee
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Publication number: 20090099290Abstract: A composition for acrylic artificial stone, the composition including a (meth)acrylic monomer and an inorganic material. At least one of the (meth)acrylic monomer and the inorganic material may be contained in a component generated by decomposing a polymeric (meth)acrylic resin.Type: ApplicationFiled: October 8, 2008Publication date: April 16, 2009Inventors: Myeong Cheon Jeon, Hyeong Gyu Ahn, Jong Gap Kim, Hae Mun Jung, Seung Hwa Jeong, Bang Jun Park
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Publication number: 20080266944Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaoyu Chen, Donghua Liu, Sung Mun Jung, Swee Tuck Woo, Rachel Low, Louis Lim, Siow Lee Chwa
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Patent number: 7439603Abstract: The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.Type: GrantFiled: February 2, 2007Date of Patent: October 21, 2008Assignee: Dongbu Hitek Co., Ltd.Inventors: Sung Mun Jung, Jum Soo Kim
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Publication number: 20080196266Abstract: A ductless dryer includes a main body, a drum rotatably installed at the main body, a heat exchanger for removing moisture from air exhausted from the drum, a circulation duct to flow the air exhausted from the drum into the heat exchanger, an exhaust duct to flow the air exhausted from the heat exchanger outside the dryer; and a noise reduction portion to attenuate noise propagation through the exhaust duct. As the ductless dryer is provided with the noise reduction portion, the noise propagation through the exhaust duct exposed into the room and the noise of the entire ductless dryer can be attenuated at the same time, whereby a quieter room environment can be provided.Type: ApplicationFiled: February 19, 2008Publication date: August 21, 2008Inventors: Han-Yong Jung, Seung-Phyo Ahn, Sang-Ik Lee, Kyung-Mun Jung, Yoon-Seob Eom, Yang-Ho Kim, Jea-Hyuk Wee, Byeong-Jo Ryoo, Sung-Ho Song