Abstract: A signal generating device includes a digital signal processing unit, M sub DACs of which an analog bandwidth is fB, M being an integer equal to or greater than 2, a broadband analog signal generating unit configured to generate a broadband analog signal that includes a component of a frequency of (M-1)fB or more by using M analog signals output from the M sub DACs. The digital signal processing unit includes components for generating M original divided signals that correspond to signals obtained by dividing a desired output signal into M portions on a frequency axis and down-converting the portions to the baseband, components for generating M folded divided signals by folding back the M original divided signals on the frequency axis, and a 2M×M filter that takes the original divided signals and the folded divided signals as inputs and outputs M composite signals to be transmitted to the M sub DACs. The 2M×M filter can set a response function independently for each of 2M2 combinations of input and output.

Abstract: A wide-band analog input signal is converted into a digital output signal on the basis of a band division method without the need for filter circuits. An analog processing block Aj (j=2 to N, where N is an integer) down-converts an analog input signal Sx using a cutoff frequency fj-1 of a channel CHj-1 and A/D-converts an analog signal Saj acquired as a result. A digital processing block Bj doubles the signal strength of a first digital signal S1j acquired by Aj, subtracts a third digital signal S3j-1 of the channel CHj-1 from a second digital signal S2j acquired as a result, up-converts the acquired third digital signal S3j using the cutoff frequency fj-1, and outputs the result to an adder as a channel output signal Syj of a corresponding channel CHj.

Abstract: In a distributed amplifier, a plurality of cascode amplifiers connected in parallel between an input side transmission line and an output side transmission line are provided, a transmission line is connected to an input terminal of an output transistor of each of the amplifiers, and a bias potential is applied from a bias circuit to the input terminal of the output transistor via the transmission line.

Abstract: A digital-to-analog converter includes a core circuit including a plurality of input terminals for multi-bit digital signals, an output terminal for an analog signal, a plurality of constant current sources, a plurality of switch circuits connected in series to respective constant current sources of the plurality of constant current sources, and a load resistor connected to the output terminal. The core circuit being configured to select whether or not to allow a current to flow through each of the plurality of switch circuits based on the multi-bit digital signals and output a voltage generated by allowing the current flowing through each of the plurality of switch circuits to flow through the load resistor from the output terminal as an analog signal.

Abstract: A digital signal process unit includes a first cancel signal generation unit and a second cancel signal generation unit. The first cancel signal generation unit generates, as a first cancel signal component, a cancel signal component corresponding to an image signal included in an analog signal output from a mixer. The second cancel signal generation unit generates, as a second cancel signal component, a cancel signal component corresponding to a leakage signal generated between an input and output of the mixer. The digital signal process unit includes subtractors for subtracting the first cancel signal component and the second cancel signal component from a signal component corresponding to a frequency band divided from an input signal to obtain a digital signal.

Abstract: A reception-side IC chip (1a) includes a pad (15) which is connected to a transmission line (2) which is outside the chip and has a characteristic impedance Z0 of 50 ?, a signal line (16), one end of which is connected to the pad (15), a reception-side input unit circuit (10) configured to receive a signal (S) transmitted from a transmission-side IC chip via the transmission line (2), a 50-? termination resistor (11), for impedance matching, which is connected between a predetermined voltage and the other end of the signal line (16) and is configured to terminate the transmission line (2), and a capacitor (12) inserted between a node (A) of the signal line (16) and the termination resistor (11) and an input terminal (In) of the reception-side input unit circuit (10). A DC-blocking circuit is formed by the capacitor (12).

Abstract: A digital-to-analog converter includes a core circuit including a plurality of input terminals for multi-bit digital signals, an output terminal for an analog signal, a plurality of constant current sources, a plurality of switch circuits connected in series to respective constant current sources of the plurality of constant current sources, and a load resistor connected to the output terminal. The core circuit being configured to select whether or not to allow a current to flow through each of the plurality of switch circuits based on the multi-bit digital signals and output a voltage generated by allowing the current flowing through each of the plurality of switch circuits to flow through the load resistor from the output terminal as an analog signal.

Abstract: A CMOS inverter circuit is provided as a circuit to modulate a current flowing into a laser diode on the basis of a digital signal. An amplitude of a current flowing in a PMOSFET in the CMOS inverter circuit is made to contribute to an amplitude of the current flowing into the laser diode, to reduce an input amplitude.

Abstract: A driver circuit 11 includes a plurality of cascode-connected NMOS transistors, a modulating signal VGN1 is applied to a gate terminal of a lowermost stage transistor TN1 located at a lowermost stage out of the NMOS transistors, and an upper stage bias potential VGN2 that is a sum of a minimum gate-source voltage VGN1min and a maximum drain-source voltage VDS1max of a transistor (TN1) located immediately below an upper stage transistor located at an upper stage above the lowermost stage transistor of the NMOS transistors is applied to the upper stage transistor TN2.

Abstract: A connection structure (3) of a high-frequency transmission line according to this invention includes a columnar central conductor (7) having one end connected to a coaxial line and the other end connected to a planar transmission line, a first outer conductor (41) arranged on a side of the one end of the central conductor coaxially with the central conductor, a first dielectric body (42) filled between the first outer conductor and the central conductor, a second outer conductor (61) arranged on a side of the other end of the central conductor coaxially with the central conductor, a second dielectric body (62) filled between the second outer conductor and the central conductor, a third outer conductor (51) arranged between the first outer conductor and the second outer conductor coaxially with the central conductor, and a third dielectric body (52) filled between the third outer conductor and the central conductor.

Abstract: An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (IEE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (REA1, REA2, REA3, REA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of “REA·IEE?the amplitude of an input analog signal” is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).

Abstract: A driver circuit 11 includes a plurality of cascode-connected NMOS transistors, a modulating signal VGN1 is applied to a gate terminal of a lowermost stage transistor TN1 located at a lowermost stage out of the NMOS transistors, and an upper stage bias potential VGN2 that is a sum of a minimum gate-source voltage VGN1min and a maximum drain-source voltage VDS1max of a transistor (TN1) located immediately below an upper stage transistor located at an upper stage above the lowermost stage transistor of the NMOS transistors is applied to the upper stage transistor TN2.

Abstract: An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10-R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.

Abstract: A connection structure (3) of a high-frequency transmission line according to this invention includes a columnar central conductor (7) having one end connected to a coaxial line and the other end connected to a planar transmission line, a first outer conductor (41) arranged on a side of the one end of the central conductor coaxially with the central conductor, a first dielectric body (42) filled between the first outer conductor and the central conductor, a second outer conductor (61) arranged on a side of the other end of the central conductor coaxially with the central conductor, a second dielectric body (62) filled between the second outer conductor and the central conductor, a third outer conductor (51) arranged between the first outer conductor and the second outer conductor coaxially with the central conductor, and a third dielectric body (52) filled between the third outer conductor and the central conductor.

Abstract: In the conventional technique, only an output having a bandwidth identical to the bandwidth of individual DACs has been obtained even by using a plurality of DACs. Also, even when the output of a bandwidth broader than the individual DAC is obtained, there has been a problem associated with asymmetricity of a circuit configuration. In a signal generating device of the present invention, a plurality of normal DACs are combined to realize an analog output of a broader bandwidth beyond the output bandwidth of the individual DACs, and the problem of the asymmetricity of the circuit configuration is also resolved. A desired signal is separated into a low-frequency signal and a high-frequency signal in a frequency domain, and a series of operation of constant (r)-folding the amplitude of the high-frequency signal and shifting it on the frequency axis to superimpose it on the low-frequency signal are made in a digital domain. The output of each DAC is switched by an analog multiplexer.

Abstract: In the conventional technique, only an output having a bandwidth identical to the bandwidth of individual DACs has been obtained even by using a plurality of DACs. Also, even when the output of a bandwidth broader than the individual DAC is obtained, there has been a problem associated with asymmetricity of a circuit configuration. In a signal generating device of the present invention, a plurality of normal DACs are combined to realize an analog output of a broader bandwidth beyond the output bandwidth of the individual DACs, and the problem of the asymmetricity of the circuit configuration is also resolved. A desired signal is separated into a low-frequency signal and a high-frequency signal in a frequency domain, and a series of operation of constant (r)-folding the amplitude of the high-frequency signal and shifting it on the frequency axis to superimpose it on the low-frequency signal are made in a digital domain. The output of each DAC is switched by an analog multiplexer.

Abstract: An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (IEE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (REA1, REA2, REA3, REA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of “REA·IEE?the amplitude of an input analog signal” is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).

Abstract: In the conventional technique, only an output having a bandwidth identical to the bandwidth of individual DACs has been obtained even by using a plurality of DACs. Also, even when the output of a bandwidth broader than the individual DAC is obtained, there has been a problem associated with asymmetricity of a circuit configuration. In a signal generating device of the present invention, a plurality of normal DACs are combined to realize an analog output of a broader bandwidth beyond the output bandwidth of the individual DACs, and the problem of the asymmetricity of the circuit configuration is also resolved. A desired signal is separated into a low-frequency signal and a high-frequency signal in a frequency domain, and a series of operation of constant (r)-folding the amplitude of the high-frequency signal and shifting it on the frequency axis to superimpose it on the low-frequency signal are made in a digital domain. The output of each DAC is switched by an analog multiplexer.

Abstract: An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10-R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.

Abstract: A vector sum phase shifter includes a 90° phase shifter (1) which generates an in-phase signal (VINI) and a quadrature signal (VINQ) from an input signal (VIN), a four-quadrant multiplier (2I) which changes the amplitude of the in-phase signal (VINI) based on a control signal (CI), a four-quadrant multiplier (2Q) which changes the amplitude of the quadrature signal (VINQ) based on a control signal (CQ), a combiner (3) which combines the in-phase signal (VINI) and the quadrature signal (VINQ), and a control circuit (4). The control circuit (4) includes a voltage generator which generates a reference voltage, and a differential amplifier which outputs the difference signal between a control voltage (VC) and the reference voltage as the control signal (CI, CQ). The differential amplifier performs an analog operation of converting the control voltage (VC) into the control signal (CI, CQ) similar to a sine wave or a cosine wave.