Abstract: A voltage generator (400) includes a resistor ladder including resistors (4000-4008) which divide a supplied voltage to generate a plurality of reference voltages, a resistor (4009) provided between a power supply voltage (VCC) and one terminal of the resistor ladder, and a resistor (4010) provided between a power supply voltage (VEE) and the other terminal of the resistor ladder.

Abstract: Two D flip-flops (D-FFMA, D-FFMB) output two half-rate signals (DMR-A, DMR-B) by dividing a digital input signal (DM) into two signals and retiming them based on a clock signal (CLK) and a negative-phase clock signal (CLKB). First and second switches (SM1, SM2) are driven by the two half-rate signals (DMR-A, DMR-B). Third and fourth switches (SM3, SM4) are driven by a select signal SW and a negative-phase select signal SWB that have the same frequency as that of the clock signal (CLK) but a different phase from that of the clock signal (CLK). The current supplied from a current source (1) to a load (4) thus becomes a current signal corresponding to a conversion frequency twice the frequency of the clock signal (CLK).

Abstract: Two D flip-flops (D-FFMA, D-FFMB) output two half-rate signals (DMR-A, DMR-B) by dividing a digital input signal (DM) into two signals and retiming them based on a clock signal (CLK) and a negative-phase clock signal (CLKB). First and second switches (SM1, SM2) are driven by the two half-rate signals (DMR-A, DMR-B). Third and fourth switches (SM3, SM4) are driven by a select signal SW and a negative-phase select signal SWB that have the same frequency as that of the clock signal TO (CLK) but a different phase from that of the clock signal (CLK). The current supplied from a current source (1) to a load (4) thus becomes a current signal corresponding to a conversion frequency twice the frequency of the clock signal (CLK).

Abstract: A voltage generator (400) includes a resistor ladder including resistors (4000-4008) which divide a supplied voltage to generate a plurality of reference voltages, a resistor (4009) provided between a power supply voltage (VCC) and one terminal of the resistor ladder, and a resistor (4010) provided between a power supply voltage (VEE) and the other terminal of the resistor ladder.

Abstract: A vector sum phase shifter includes a 90° phase shifter (1) which generates an in-phase signal (VINI) and a quadrature signal (VINQ) from an input signal (VIN), a four-quadrant multiplier (2I) which changes the amplitude of the in-phase signal (VINI) based on a control signal (CI), a four-quadrant multiplier (2Q) which changes the amplitude of the quadrature signal (VINQ) based on a control signal (CQ), a combiner (3) which combines the in-phase signal (VINI) and the quadrature signal (VINQ), and a control circuit (4). The control circuit (4) includes a voltage generator which generates a reference voltage, and a differential amplifier which outputs the difference signal between a control voltage (VC) and the reference voltage as the control signal (CI, CQ). The differential amplifier performs an analog operation of converting the control voltage (VC) into the control signal (CI, CQ) similar to a sine wave or a cosine wave.