Patents by Inventor Murat Kerem Akarvardar

Murat Kerem Akarvardar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10411010
    Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel Graeme Cave
  • Patent number: 10297597
    Abstract: Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric layer is formed that encapsulates a plurality of fins. A second dielectric layer is formed that surrounds the first dielectric layer and the plurality of fins. A surface of the second dielectric layer relative to a surface of the first dielectric layer. A liner is conformally deposited on the surface of the first dielectric layer and on the recessed surface of the second dielectric layer. A section of the liner is removed to expose the surface of the first dielectric layer. The exposed surface of the first dielectric layer is recessed to reveal a portion of each of the plurality of fins.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min Gyu Sung, Ruilong Xie, Chanro Park, Murat Kerem Akarvardar
  • Patent number: 10163677
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser
  • Patent number: 10062617
    Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Murat Kerem Akarvardar, Andreas Knorr
  • Patent number: 10026659
    Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: July 17, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Jody A. Fronheiser
  • Publication number: 20180182757
    Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.
    Type: Application
    Filed: January 4, 2018
    Publication date: June 28, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel Graeme Cave
  • Publication number: 20180138079
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.
    Type: Application
    Filed: December 20, 2017
    Publication date: May 17, 2018
    Inventors: Murat Kerem AKARVARDAR, Jody A. FRONHEISER
  • Publication number: 20180130656
    Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.
    Type: Application
    Filed: December 15, 2017
    Publication date: May 10, 2018
    Inventors: Judson Robert Holt, Jinping Liu, Jody Fronheiser, Bharat Krishnan, Churamani Gaire, Timothy James Mcardle, Murat Kerem Akarvardar
  • Patent number: 9960257
    Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Ajey Poovannummoottil Jacob
  • Publication number: 20180096998
    Abstract: Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric layer is formed that encapsulates a plurality of fins. A second dielectric layer is formed that surrounds the first dielectric layer and the plurality of fins. A surface of the second dielectric layer relative to a surface of the first dielectric layer. A liner is conformally deposited on the surface of the first dielectric layer and on the recessed surface of the second dielectric layer. A section of the liner is removed to expose the surface of the first dielectric layer. The exposed surface of the first dielectric layer is recessed to reveal a portion of each of the plurality of fins.
    Type: Application
    Filed: August 29, 2017
    Publication date: April 5, 2018
    Inventors: Min Gyu Sung, Ruilong Xie, Chanro Park, Murat Kerem Akarvardar
  • Patent number: 9929157
    Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel Graeme Cave
  • Patent number: 9882052
    Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert Judson Holt, Jinping Liu, Jody Fronheiser, Bharat Krishnan, Churamani Gaire, Timothy James McArdle, Murat Kerem Akarvardar
  • Patent number: 9881830
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser
  • Publication number: 20180006155
    Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Robert Judson HOLT, Jinping LIU, Jody FRONHEISER, Bharat KRISHNAN, Churamani GAIRE, Timothy James MCARDLE, Murat Kerem AKARVARDAR
  • Patent number: 9847333
    Abstract: Reducing a chance of punch-through in a FinFET structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: December 19, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kwanyong Lim, Murat Kerem Akarvardar
  • Publication number: 20170256462
    Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.
    Type: Application
    Filed: December 9, 2016
    Publication date: September 7, 2017
    Inventors: Ruilong XIE, Murat Kerem AKARVARDAR, Andreas KNORR
  • Patent number: 9716174
    Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: July 25, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Ajey Poovannummoottil Jacob
  • Patent number: 9679972
    Abstract: A semiconductor structure can include a substrate and a substrate layer. The substrate can be formed of silicon and the substrate layer can be formed of silicon germanium. Above the substrate and under the substrate layer there can be provided a multilayer substructure. The multilayer substructure can include a first layer and a second layer. The first layer can be formed of a first material and the second layer can be formed of second material. A method can include forming a multilayer substructure on a substrate, annealing the multilayer substructure, and forming a substrate layer on the multilayer substructure.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: June 13, 2017
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: Jody Fronheiser, Murat Kerem Akarvardar, Stephen Bedell, Joel Kanyandekwe
  • Publication number: 20170133406
    Abstract: A semiconductor structure, comprising a semiconductor substrate and at least one fin coupled to the semiconductor substrate, wherein the fin comprises at least two active regions and at least one insulator region, wherein all active regions and all insulator regions are stacked and each insulator region is disposed between two active regions. Methods, apparatus, and systems for forming such a semiconductor structure.
    Type: Application
    Filed: November 5, 2015
    Publication date: May 11, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Murat Kerem Akarvardar
  • Patent number: 9601383
    Abstract: A semiconductor structure for a FinFET in fabrication is provided, the structure including a bulk semiconductor substrate initially with a hard mask over the substrate. Isolation trenches between regions of the structure where the fins will be are formed prior to the fins, and filled with selectively removable sacrificial isolation material. Remains of the hard mask are removed and another hard mask formed over the structure with filled isolation trenches. Fins are then formed throughout the structure, including the regions of sacrificial isolation material, which is thereafter selectively removed.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Murat Kerem Akarvardar