Patents by Inventor Murat Kerem Akarvardar

Murat Kerem Akarvardar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240242071
    Abstract: The present disclosure provides an accelerator circuit, a semiconductor device, and a method for accelerating convolution in a convolutional neural network. The accelerator circuit includes a plurality of sub processing-element (PE) arrays, and each of the plurality of sub PE arrays includes a plurality of processing elements. The processing elements in each of the plurality of sub PE arrays implement a standard convolutional layer during a first configuration applied to the accelerator circuit, and implement a depth-wise convolutional layer during a second configuration applied to the accelerator circuit.
    Type: Application
    Filed: January 18, 2023
    Publication date: July 18, 2024
    Inventors: XIAOCHEN PENG, MURAT KEREM AKARVARDAR, XIAOYU SUN
  • Publication number: 20240203463
    Abstract: A 3D memory device is provided. The 3D memory device includes a first logic base layer, a second layer, and a third layer. The first logic base layer comprises a first type DEMUX, a plurality of second type DEMUXs coupled to the first type DEMUX, a first type MUX, and a plurality of second type MUXs coupled to the first type MUX. The second layer comprises a first group of memory units. Each of the first group of memory units is respectively coupled to a corresponding DEMUX of the plurality of second type DEMUXs and a corresponding MUX of the plurality of second type MUXs. The third layer comprises a second group of memory units. Each of the second group of memory units is respectively coupled to a corresponding DEMUX of the plurality of second type DEMUXs and a corresponding MUX of the plurality of second type MUXs.
    Type: Application
    Filed: January 17, 2023
    Publication date: June 20, 2024
    Inventors: MURAT KEREM AKARVARDAR, XIAOCHEN PENG
  • Publication number: 20240069971
    Abstract: An artificial intelligence (AI) accelerator device may include a plurality of on-chip mini buffers that are associated with a processing element (PE) array. Each mini buffer is associated with a subset of rows or a subset of columns of the PE array. Partitioning an on-chip buffer of the AI accelerator device into the mini buffers described herein may reduce the size and complexity of the on-chip buffer. The reduced size of the on-chip buffer may reduce the wire routing complexity of the on-chip buffer, which may reduce latency and may reduce access energy for the AI accelerator device. This may increase the operating efficiency and/or may increase the performance of the AI accelerator device. Moreover, the mini buffers may increase the overall bandwidth that is available for the mini buffers to transfer data to and from the PE array.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Xiaoyu SUN, Xiaochen PENG, Murat Kerem AKARVARDAR
  • Publication number: 20240053899
    Abstract: A circuit includes a data buffer configured to sequentially output first and second pluralities of bits, a plurality of memory macros having a total number, and a distribution network coupled between the data buffer and the plurality of memory macros. The distribution network separates the first plurality of bits into the total number of first subsets, and outputs each first subset to a corresponding memory macro, and either outputs an entirety of the second plurality of bits to each memory macro, or separates the second plurality of bits into a number of second subsets less than or equal to the total number, and outputs each second subset to one or more corresponding memory macros. Each memory macro outputs a product of the corresponding first subset and the one of the entirety of the second plurality of bits or the corresponding second subset of the second plurality of bits.
    Type: Application
    Filed: May 2, 2023
    Publication date: February 15, 2024
    Inventors: Xiaoyu SUN, Murat Kerem AKARVARDAR
  • Publication number: 20240028869
    Abstract: A reconfigurable processing circuit of an AI accelerator and a method of operating the same are disclosed. In one aspect, the reconfigurable processing circuit includes a first memory configured to store an input activation state, a second memory configured to store a weight, a multiplier configured to multiply the weight and the input activation state and output a product, a first multiplexer (mux) configured to, based on a first selector, output a previous sum from a previous reconfigurable processing element, a third memory configured to store a first sum, a second mux configured to, based on a second selector, output the previous sum or the first sum, an adder configured to add the product and the previous sum or the first sum to output a second sum, and a third mux configured to, based on a third selector, output the second sum or the previous sum.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xiaoyu Sun, Rawan Naous, Murat Kerem Akarvardar
  • Publication number: 20230352393
    Abstract: A semiconductor monolithic IC includes a semiconductor substrate having a rectangular shape in plan view, multiple chiplets each comprising a circuit, wherein the multiple chiplets are disposed over the semiconductor substrate and are separated from each other by die-to-die spaces filled with a dielectric material, and a plurality of conductive connection patterns electrically connecting the multiple chiplets so that a combination of the circuit of the multiple chiplet function as one functional circuit. The chip region has a larger area than a maximum exposure area of a lithography apparatus used to fabricate the first and second circuits.
    Type: Application
    Filed: June 30, 2023
    Publication date: November 2, 2023
    Inventors: Murat Kerem AKARVARDAR, Hon-Sum Philip WONG
  • Patent number: 11735515
    Abstract: A semiconductor monolithic IC includes a semiconductor substrate having a rectangular shape in plan view, multiple chiplets each comprising a circuit, wherein the multiple chiplets are disposed over the semiconductor substrate and are separated from each other by die-to-die spaces filled with a dielectric material, and a plurality of conductive connection patterns electrically connecting the multiple chiplets so that a combination of the circuit of the multiple chiplet function as one functional circuit. The chip region has a larger area than a maximum exposure area of a lithography apparatus used to fabricate the first and second circuits.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Murat Kerem Akarvardar, Hon-Sum Philip Wong
  • Patent number: 10411010
    Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel Graeme Cave
  • Patent number: 10297597
    Abstract: Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric layer is formed that encapsulates a plurality of fins. A second dielectric layer is formed that surrounds the first dielectric layer and the plurality of fins. A surface of the second dielectric layer relative to a surface of the first dielectric layer. A liner is conformally deposited on the surface of the first dielectric layer and on the recessed surface of the second dielectric layer. A section of the liner is removed to expose the surface of the first dielectric layer. The exposed surface of the first dielectric layer is recessed to reveal a portion of each of the plurality of fins.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min Gyu Sung, Ruilong Xie, Chanro Park, Murat Kerem Akarvardar
  • Patent number: 10163677
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser
  • Patent number: 10062617
    Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Murat Kerem Akarvardar, Andreas Knorr
  • Patent number: 10026659
    Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: July 17, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Jody A. Fronheiser
  • Publication number: 20180182757
    Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.
    Type: Application
    Filed: January 4, 2018
    Publication date: June 28, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel Graeme Cave
  • Publication number: 20180138079
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.
    Type: Application
    Filed: December 20, 2017
    Publication date: May 17, 2018
    Inventors: Murat Kerem AKARVARDAR, Jody A. FRONHEISER
  • Publication number: 20180130656
    Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.
    Type: Application
    Filed: December 15, 2017
    Publication date: May 10, 2018
    Inventors: Judson Robert Holt, Jinping Liu, Jody Fronheiser, Bharat Krishnan, Churamani Gaire, Timothy James Mcardle, Murat Kerem Akarvardar
  • Patent number: 9960257
    Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Ajey Poovannummoottil Jacob
  • Publication number: 20180096998
    Abstract: Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric layer is formed that encapsulates a plurality of fins. A second dielectric layer is formed that surrounds the first dielectric layer and the plurality of fins. A surface of the second dielectric layer relative to a surface of the first dielectric layer. A liner is conformally deposited on the surface of the first dielectric layer and on the recessed surface of the second dielectric layer. A section of the liner is removed to expose the surface of the first dielectric layer. The exposed surface of the first dielectric layer is recessed to reveal a portion of each of the plurality of fins.
    Type: Application
    Filed: August 29, 2017
    Publication date: April 5, 2018
    Inventors: Min Gyu Sung, Ruilong Xie, Chanro Park, Murat Kerem Akarvardar
  • Patent number: 9929157
    Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel Graeme Cave
  • Patent number: 9881830
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser
  • Patent number: 9882052
    Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert Judson Holt, Jinping Liu, Jody Fronheiser, Bharat Krishnan, Churamani Gaire, Timothy James McArdle, Murat Kerem Akarvardar