Abstract: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.

Abstract: A method for forming fine patterns of a semiconductor device is disclosed. The method includes forming an etch film on a substrate, forming a protection film on the etch film, forming a hard mask layer on the protection film, and forming a plurality of first mask patterns characterized by a first pitch on the hard mask layer. The method further comprises forming a plurality of second mask patterns, forming hard mask patterns exposing portions of the protection film by etching the hard mask layer using the first and second mask patterns as an etch mask, and removing the first and second mask patterns. The method still further comprises exposing portions of the etch film and forming a plurality of fine patterns characterized by a second pitch equal to half of the first pitch by etching the etch film using at least the hard mask patterns as an etch mask.

Abstract: The present invention is directed to receiving a point-to-multipoint service while receiving a dedicated service in a wireless communication system. A mobile terminal receives radio link configuration information from a network for establishing a radio link with a cell in order to receive the dedicated service. While receiving the radio link configuration information, the mobile terminal also receives directly from the network point-to-multipoint control channel and/or point-to-multipoint indication channel configuration information of the cell for receiving the point-to-multipoint service.

Abstract: The present invention is directed to interrupting use of a frequency layer convergence scheme that favors selection of a cell on a preferred frequency of a joined point-to-multipoint service, specifically, a mobile terminal that has joined a point-to-multipoint service having a preferred frequency uses a frequency layer convergence scheme for selecting a cell, the frequency layer convergence scheme favors the selection of a cell on the preferred frequency layer, however, use of the frequency layer convergence scheme is interrupted upon an occurrence of a trigger.

Abstract: The present invention is directed to interrupting use of a frequency layer convergence scheme that favors selection of a cell on a preferred frequency of a joined point-to-multipoint service. Specifically, a mobile terminal that has joined a point-to-multipoint service having a preferred frequency uses a frequency layer convergence scheme for selecting a cell. The frequency layer convergence scheme favors the selection of a cell on the preferred frequency layer. However, use of the frequency layer convergence scheme is interrupted upon an occurrence of a trigger.

Abstract: A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern.

Abstract: A method of forming fine patterns of a semiconductor device includes double etching by changing a quantity of producing polymer by-products to etch a film with different thicknesses in regions having different pattern densities. In a first etching, reactive ion etching (RIE) is performed upon a buffer layer and a hardmask layer both in a low-density pattern region and a high-density pattern region under a first etching ambient until an etch film is exposed in the low-density pattern region using mask patterns as an etch mask. In second etching for forming the hardmask patterns, using the mask patterns as an etch mask, the hardmask layer is etched until the etch film is exposed in the high-density pattern region while accumulating polymer by-products on the etch film in the low-density pattern region under a second etching ambient having polymer by-products produced greater than in the first etching ambient.

Abstract: The present invention is a method for identifying a point-to-multipoint service. When a plurality of point-to-multipoint services are multiplexed to one transport channel, a temporary service identifier (TSI) is defined and inserted into a MAC PDU header so that the plurality of point-to-multipoint services can be individually identified. Thus, overhead is reduced and multiple services having a different quality of service (QoS) or multiple streams of different QoS in the same service can be handled and provided to a mobile terminal.

Abstract: A method for forming hard mask patterns includes, sequentially forming first, second, and third hard mask layers formed of materials having different etching selectivities on a substrate, forming first sacrificial patterns having a first pitch therebetween on the third hard mask layer, forming fourth hard mask patterns with a second pitch between the first sacrificial patterns, the second pitch being substantially equal to about ½ of the first pitch, patterning the third hard mask layer to form third hard mask patterns using the fourth hard mask patterns as an etch mask, patterning the second hard mask layer to form second hard mask patterns using the third and fourth hard mask patterns as an etch mask, and patterning the first hard mask layer to form first hard mask patterns with the second pitch therebetween using the second and third hard mask patterns as an etch mask.

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern.

Abstract: A method for forming fine patterns of a semiconductor device is disclosed. The method includes forming an etch film on a substrate, forming a protection film on the etch film, forming a hard mask layer on the protection film, and forming a plurality of first mask patterns characterized by a first pitch on the hard mask layer. The method further comprises forming a plurality of second mask patterns, forming hard mask patterns exposing portions of the protection film by etching the hard mask layer using the first and second mask patterns as an etch mask, and removing the first and second mask patterns. The method still further comprises exposing portions of the etch film and forming a plurality of fine patterns characterized by a second pitch equal to half of the first pitch by etching the etch film using at least the hard mask patterns as an etch mask.

Abstract: A method of fabricating a semiconductor device which prevents a pitting phenomenon from occurring on a gate insulating layer is provided.

Abstract: The invention relates to a method for settling an error in a radio link control entity which processes data transmitted by a cellular network to a user equipment, comprising the following steps: the user equipment receives a message from a control entity of the cellular network, said message including data identifying the radio link control entity which is in error, the user equipment re-initializes the radio link control entity according to the data included in the message. Particular application for settling unrecoverable errors affecting a radio link controller of a user equipment in a UMTS network.

Abstract: Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer.

Abstract: A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that the third layer includes a top surface having a recess formed between two adjacent first line patterns. A second hard mask pattern including a plurality of second line patterns each extending in the first direction within the recess is formed. Then, the third layer is anisotropically etched to selectively expose an etch target layer between the first line patterns and the second line patterns. Then, the etch target layer is anisotropically etched using the first hard mask pattern and the second hard mask pattern as an etch mask.

Abstract: Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.

Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided.

Abstract: Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.