Abstract: A metal contact structure of a semiconductor device and a method for forming the same, wherein an upper conductive layer is formed by etching a metal layer, which fills a contact hole and is formed on the entire surface of an interlayer dielectric film and etching is stopped when barrier metal layers under the metal layer is exposed. Then, after forming spacers on the sidewalls of an upper conductive layer, the barrier metal layers (a barrier layer and an ohmic layer) are removed using the spacers as etching masks. Therefore, it is possible to prevent problems due to etch mask misalignment, such as 1) an etching gas of the metal layer permeating through the ohmic layer and 2) defects such as contact resistance changes that occur when spacers cover a contact hole even though the upper conductive layer does not completely cover that contact hole.

Abstract: There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant

Abstract: A semiconductor device having a self-aligned contact and a method for forming the same, including a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region; a self-aligned contact exposing a portion of the self-aligned contact region; a first insulating layer formed on the semiconductor substrate that exposes the self-aligned contact; conductive patterns formed on the first insulating layer and spaced apart from each other; spacers formed on sidewalls of each of the conductive patterns; a second insulating layer formed over the first insulating layer that exposes the self-aligned contact; a third insulating layer formed between the second insulating layer and the spacer; a fourth insulating layer formed over the non-self-aligned contact region and on sidewalls of the spacers over the self-aligned contact region; and a fifth insulating layer formed on a portion of the fourth insulating layer over the non-self-aligned contact region.

Abstract: Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device.

Abstract: A preferred method of forming a metal line in a semiconductor memory device includes depositing first, second, and third metal layers on a semiconductor substrate. A fourth layer is deposited on the third metal layer. The fourth layer is etched to form a hard mask. A first cleaning process is performed using a first cleaning agent, a second cleaning agent, or both. The third metal layer is etched according to the hard mask. A second cleaning process is performed using the first cleaning agent or the first and second cleaning agents. The first and second metal layers are etched simultaneously according to the hard mask. A third cleaning process is performed using the second cleaning agent.

Abstract: A semiconductor device having a self-aligned contact and a method for forming the same, including a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region; a self-aligned contact exposing a portion of the self-aligned contact region; a first insulating layer formed on the semiconductor substrate that exposes the self-aligned contact; conductive patterns formed on the first insulating layer and spaced apart from each other; spacers formed on sidewalls of each of the conductive patterns; a second insulating layer formed over the first insulating layer that exposes the self-aligned contact; a third insulating layer formed between the second insulating layer and the spacer; a fourth insulating layer formed over the non-self-aligned contact region and on sidewalls of the spacers over the self-aligned contact region; and a fifth insulating layer formed on a portion of the fourth insulating layer over the non-self-aligned contact region.

Abstract: There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant

Abstract: Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device.

Abstract: A semiconductor device having a self-aligned contact and a method for forming the same, including a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region; a self-aligned contact exposing a portion of the self-aligned contact region; a first insulating layer formed on the semiconductor substrate that exposes the self-aligned contact; conductive patterns formed on the first insulating layer and spaced apart from each other; spacers formed on sidewalls of each of the conductive patterns; a second insulating layer formed over the first insulating layer that exposes the self-aligned contact; a third insulating layer formed between the second insulating layer and the spacer; a fourth insulating layer formed over the non-self-aligned contact region and on sidewalls of the spacers over the self-aligned contact region; and a fifth insulating layer formed on a portion of the fourth insulating layer over the non-self-aligned contact region.

Abstract: A semiconductor device having a conductive layer side surface slope of at least 90° and a method for making the same is provided. An interlayer dielectric film and a conductive layer are formed on a semiconductor substrate. The interlayer dielectric film has a side surface slope defining a hole of less than 90°. A conductive layer having a side surface slope of at least 90° is formed in the hole defined by the interlayer dielectric film. The semiconductor device is manufactured by coating a preliminary film on a semiconductor substrate. Patterning the preliminary film forms a preliminary film pattern having a side surface slope of 90°. The interlayer dielectric film is formed on the semiconductor substrate and the preliminary film pattern. Removing some of the interlayer dielectric film exposes an upper surface of the preliminary film pattern.

Abstract: A metal contact structure of a semiconductor device and a method for forming the same, wherein an upper conductive layer is formed by etching a metal layer, which fills a contact hole and is formed on the entire surface of an interlayer dielectric film and etching is stopped when barrier metal layers under the metal layer is exposed. Then, after forming spacers on the sidewalls of an upper conductive layer, the barrier metal layers (a barrier layer and an ohmic layer) are removed using the spacers as etching masks. Therefore, it is possible to prevent problems due to etch mask misalignment, such as 1) an etching gas of the metal layer permeating through the ohmic layer and 2) defects such as contact resistance changes that occur when spacers cover a contact hole even though the upper conductive layer does not completely cover that contact hole.

Abstract: A preferred method of forming a metal line in a semiconductor memory device includes depositing first, second, and third metal layers on a semiconductor substrate. A fourth layer is deposited on the third metal layer. The fourth layer is etched to form a hard mask. A first cleaning process is performed using a first cleaning agent, a second cleaning agent, or both. The third metal layer is etched according to the hard mask. A second cleaning process is performed using the first cleaning agent or the first and second cleaning agents. The first and second metal layers are etched simultaneously according to the hard mask. A third cleaning process is performed using the second cleaning agent.

Abstract: There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant

Abstract: A hemispherical grain (HSG) capacitor having HSGs on at least a part of the surface of capacitor lower electrodes, and a method of forming the same. In the capacitor, lower electrodes are formed of at least two amorphous silicon layers including an amorphous silicon layer doped with a high concentration of impurities and an amorphous silicon layer doped with a low concentration of impurities, and HSGs are formed, wherein the size of the hemispherical grains can be adjusted such that the size of HSGs formed on the inner surface of a U-shaped lower electrode or on the top of a stacked lower electrode is larger than that of HSGs formed on the outer surface of the U-shaped lower electrode or on the sidews of the stacked lower electrode. Thus, bridging between neighboring lower electrodes can be avoided by appropriately adjusting the size of HSGs, resulting in uniform capacitance wafer-to-wafer and within a wafer. The mechanical strength of the U-shaped lower electrode can also be enhanced.

Abstract: A semiconductor device having a self-aligned contact and a method of manufacturing the same. The device comprises a semiconductor substrate and two spaced apart conductor structures formed on the substrate. Each of the conductor structures includes a first conductive layer covered with a silicon nitride mask layer. Silicon oxide spacers are formed on the sides of each conductor structure to a height lower than the top surface of the silicon nitride mask layer. Silicon nitride spacers are formed on the sides of each conductor structure and the surface of the silicon oxide spacers. Over the conductor structures and substrate, there is formed an insulating layer of silicon oxide having a self-aligned contact hole exposing the silicon nitride spacers and partially extending over each conductor structure. The self-aligned contact hole is filled up with a second conductive layer self-aligned to the conductor structures.

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided.

Abstract: A semiconductor device having a self-aligned contact and a method for fabricating the same are provided. The semiconductor device includes a plurality of conductive patterns formed to be adjacent to one another by sequentially stacking and patterning a first conductive layer and a mask layer on a particular underlying layer. A first insulation layer fills a gap between adjacent conductive layer patterns such that the upper portion of each conductive layer pattern is exposed. A second insulation layer having a spacer shape is formed on the sides of each conductive layer pattern exposed above the first insulation layer. A second conductive layer fills a contact hole which is self-aligned with respect to the second insulation layers between adjacent conductive layer patterns and passes through the first insulation layer.